Intel Xeon® Processor X3430 (8M Cache, 2.40 GHz) BX80605X3430 User Manual
Product codes
BX80605X3430
Intel® Xeon® Processor 3400 Series Datasheet, Volume 2
29
Processor Integrated I/O (IIO) Configuration Registers
treated as static in the sense that they will not be changed without the decode control
bits being clear. Registers outside of this standard space will be noted as dynamic when
appropriate.
bits being clear. Registers outside of this standard space will be noted as dynamic when
appropriate.
3.3.2
Configuration Register Map
software. Each PCI Express configuration space has three regions:
• Standard PCI Header — This region is the standard PCI-to-PCI bridge header
providing legacy OS compatibility and resource management.
• PCI Device Dependent Region — This region is also part of standard PCI
configuration space and contains the PCI capability structures and other port
specific registers. For the IIO, the supported capabilities are:
specific registers. For the IIO, the supported capabilities are:
— SVID/SDID Capability
— Message Signalled Interrupts
— Power Management
— Message Signalled Interrupts
— Power Management
Figure 3-1. DMI Port (Device 0) and PCI Express* Root Ports Type 1 Configuration Space
0 0 h
4 0 h
1 0 0 h
F F F h
M S I C a p a b ilit y
P 2 P '
C A P _ P T R
P C I E C a p a b ilit y
Ex
te
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at
io
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S
pa
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PC
I
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ev
ic
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PC
I
H
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r
P M C a p a b ilit y
S V I D / S D I D C a p a b ilit y