Intel Celeron M 2.4GHz RH80532NC056256 User Manual
Product codes
RH80532NC056256
R
32
Specification Update
V47.
BTS(Branch Trace Store) and PEBS(Precise Event Based Sampling) May Update
Memory outside the BTS/PEBS Buffer
Memory outside the BTS/PEBS Buffer
Problem: If the BTS/PEBS buffer is defined such that:
·
The difference between BTS/PEBS buffer base and BTS/PEBS absolute maximum is not an
integer multiple of the corresponding record sizes
integer multiple of the corresponding record sizes
·
BTS/PEBS absolute maximum is less than a record size from the end of the virtual address space
·
The record that would cross BTS/PREBS absolute maximum will also continue past the end of
the virtual address space
the virtual address space
Implication: Software that uses BTS/PEBS near the 4-G boundary (IA32) or 2^64 boundary (EMT64T mode), and
defines the buffer such that it does not hold an integer multiple of records can update memory outside
the BTS/PEBS buffer.
the BTS/PEBS buffer.
Workaround: Define BTS/PEBS buffer such that BTS/PEBS absolute maximum minus BTS/PEBS buffer base is
integer multiple of the corresponding record sizes as recommended in the IA-32 Intel
®
Architecture
Software Developer’s Manual Volume 3.
Status:
For the steppings affected see the Summary Tables of Changes.
V48.
Memory Ordering Failure May Occur with Snoop Filtering Third- Party Agents
after Issuing and Completing a BWIL (Bus Write Invalidate Line) or BLW (Bus
Locked Write) Transaction
after Issuing and Completing a BWIL (Bus Write Invalidate Line) or BLW (Bus
Locked Write) Transaction
Problem:
Under limited circumstances, the processors may, after issuing and completing a BWIL or BLW
transaction, retain data from the addressed cache line in shared state even though the specification
requires complete invalidation. This data retention may also occur when a BWIL transaction’s self-
snooping yields HITM snoop results.
requires complete invalidation. This data retention may also occur when a BWIL transaction’s self-
snooping yields HITM snoop results.
Implication: A system may suffer memory ordering failures if its central agent incorporates coherence sequencing
which depends on full self-invalidation of the cache line associated with (1) BWIL and BLW
transactions, or (2) all HITM snoop results without regard to the transaction type and snoop results’
source.
transactions, or (2) all HITM snoop results without regard to the transaction type and snoop results’
source.
Workaround: 1. The central agent can issue a bus cycle that causes a cache line to be invalidated (Bus Read Invalidate
Line (BRIL) or BWIL transaction) in response to a processor-generated BWIL (or BLW) transaction to
insure complete invalidation of the associated cache line. If there are no intervening processor-
originated transactions to that cache line, the central agent’s invalidating snoop will get a clean snoop
result.
insure complete invalidation of the associated cache line. If there are no intervening processor-
originated transactions to that cache line, the central agent’s invalidating snoop will get a clean snoop
result.
Or
2. Snoop filtering central agents can:
a. Not use processor-originated BWIL or BLW transactions to update their snoop filter
information, or
information, or
b. Update the associated cache line state information to shared state on the originating bus
(rather than invalid state) in reaction to a BWIL or BLW.
(rather than invalid state) in reaction to a BWIL or BLW.
Status:
For the steppings affected, see the Summary Tables of Changes.