Motorola MPC8260 User Manual
4-18
MPC8260 PowerQUICC II UserÕs Manual
MOTOROLA
Part II. ConÞguration and Reset
The SICR register bits are described in Table 4-4.
4.3.1.2 SIU Interrupt Priority Register (SIPRR)
The SIU interrupt priority register (SIPRR), shown in Figure 4-11, deÞnes the priority
between IRQ1ÐIRQ6, PIT, and TMCNT.
between IRQ1ÐIRQ6, PIT, and TMCNT.
Table 4-4. SICR Field Descriptions
Bits
Name
Description
0Ð1
Ñ
Reserved, should be cleared.
2Ð7
HP
Highest priority. SpeciÞes the 6-bit interrupt number of the single interrupt controller interrupt source
that is advanced to the highest priority in the table. HP can be modiÞed dynamically. To retain the
original priority, program HP to the interrupt number assigned to XSIU1.
that is advanced to the highest priority in the table. HP can be modiÞed dynamically. To retain the
original priority, program HP to the interrupt number assigned to XSIU1.
8Ð14
Ñ
Reserved, should be cleared.
14
GSIU Group SIU. Selects the relative XSIU priority scheme. It cannot be changed dynamically.
0 Grouped. The XSIUs are grouped by priority at the top of the table.
1 Spread. The XSIUs are spread by priority in the table.
1 Spread. The XSIUs are spread by priority in the table.
15
SPS
Spread priority scheme. Selects the relative YCC priority scheme. It cannot be changed dynamically.
0 Grouped. The YCCs are grouped by priority at the top of the table.
1 Spread. The YCCs are spread by priority in the table.
0 Grouped. The YCCs are grouped by priority at the top of the table.
1 Spread. The YCCs are spread by priority in the table.
Bits
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Field
XS1P
XS2P
XS3P
XS4P
Ñ
Reset
000
001
010
011
0000
R/W
R/W
Addr
Bits
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Field
XS5P
XS6P
XS7P
XS8P
Ñ
Reset
100
101
110
111
0000
R/W
R/W
Addr
0x10C12
Figure 4-11. SIU Interrupt Priority Register (SIPRR)