Motorola MPC8260 User Manual
5-8
MPC8260 PowerQUICC II UserÕs Manual
MOTOROLA
Part II. ConÞguration and Reset
5.4.1 Hard Reset ConÞguration Word
The contents of the hard reset conÞguration word are shown in Figure 5-3.
Bits
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Field
EARB EXMC CDIS EBM
BPS
CIP
ISPS
L2CPC
DPPC
Ñ
ISB
Reset
0000_0000_0000_0000
Bits
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Field
BMS
BBD
MMR
LBPC
APPC
CS10PC
Ñ
MODCK_H
Reset
0000_0000_0000_0000
Figure 5-3. Hard Reset Configuration Word
Table 5-7. Hard Reset Configuration Word Field Descriptions
Bits
Name
Description
0
EARB
External arbitration. DeÞnes the initial value for ACR[EARB]. If EARB = 1, external arbitration is
assumed. See Section 4.3.2.2, Ò60x Bus Arbiter ConÞguration Register (PPC_ACR).Ó
assumed. See Section 4.3.2.2, Ò60x Bus Arbiter ConÞguration Register (PPC_ACR).Ó
1
EXMC
External MEMC. DeÞnes the initial value of BR0[EMEMC]. If EXMC = 1, an external memory
controller is assumed. See Section 10.3.1, ÒBase Registers (BRx).Ó
controller is assumed. See Section 10.3.1, ÒBase Registers (BRx).Ó
2
CDIS
Core disable. DeÞnes the initial value for the SIUMCR[CDIS].
0 The core is active. See Section 4.3.2.6, ÒSIU Module ConÞguration Register (SIUMCR).Ó
1 The core is disabled. In this mode the MPC8260 functions as a slave.
0 The core is active. See Section 4.3.2.6, ÒSIU Module ConÞguration Register (SIUMCR).Ó
1 The core is disabled. In this mode the MPC8260 functions as a slave.
3
EBM
External bus mode. DeÞnes the initial value of BCR[EBM]. See Section 4.3.2.1, ÒBus
ConÞguration Register (BCR).Ó
ConÞguration Register (BCR).Ó
4Ð5
BPS
Boot port size. DeÞnes the initial value of BR0[PS], the port size for memory controller bank 0.
00 64-bit port size
01 8-bit port size
10 16-bit port size
11 32-bit port size
See Section 10.3.1, ÒBase Registers (BRx).Ó
00 64-bit port size
01 8-bit port size
10 16-bit port size
11 32-bit port size
See Section 10.3.1, ÒBase Registers (BRx).Ó
6
CIP
Core initial preÞx. DeÞnes the initial value of MSR[IP]. Exception preÞx. The setting of this bit
speciÞes whether an exception vector offset is prepended with Fs or 0s. In the following
description, nnnnn is the offset of the exception vector.
0 MSR[IP] = 1 (default). Exceptions are vectored to the physical address 0xFFFn_nnnn
1 MSR[IP] = 0 Exceptions are vectored to the physical address 0x000n_nnnn.
speciÞes whether an exception vector offset is prepended with Fs or 0s. In the following
description, nnnnn is the offset of the exception vector.
0 MSR[IP] = 1 (default). Exceptions are vectored to the physical address 0xFFFn_nnnn
1 MSR[IP] = 0 Exceptions are vectored to the physical address 0x000n_nnnn.
7
ISPS
Internal space port size. DeÞnes the initial value of BCR[ISPS]. Setting ISPS conÞgures the
MPC8260 to respond to accesses from a 32-bit external master to its internal space. See
Section 4.3.2.1, ÒBus ConÞguration Register (BCR).Ó
MPC8260 to respond to accesses from a 32-bit external master to its internal space. See
Section 4.3.2.1, ÒBus ConÞguration Register (BCR).Ó
8Ð9
L2CPC
L2 cache pins conÞguration. DeÞnes the initial value of SIUMCR[L2CPC]. See Section 4.3.2.6,
ÒSIU Module ConÞguration Register (SIUMCR).Ó
ÒSIU Module ConÞguration Register (SIUMCR).Ó
10Ð11
DPPC
Data parity pin conÞguration. DeÞnes the initial value of SIUMCR[DPPC]. For more details refer
to Section 4.3.2.6, ÒSIU Module ConÞguration Register (SIUMCR).Ó
to Section 4.3.2.6, ÒSIU Module ConÞguration Register (SIUMCR).Ó
12
Ñ
Reserved, should be cleared.