Motorola MPC8260 User Manual
MOTOROLA
Chapter 5. Reset
5-9
Part II. ConÞguration and Reset
5.4.2 Hard Reset ConÞguration Examples
This section presents some examples of hard reset conÞgurations in different systems.
5.4.2.1 Single MPC8260 with Default ConÞguration
This is the simplest conÞguration scenario. It can be used if the default values achieved by
clearing the hard reset conÞguration word are desired. This is applicable only for systems
using single-MPC8260 bus mode (as opposed to 60x bus mode). To enter this mode, tie
RSTCONF to V
clearing the hard reset conÞguration word are desired. This is applicable only for systems
using single-MPC8260 bus mode (as opposed to 60x bus mode). To enter this mode, tie
RSTCONF to V
CC
as shown in Figure 5-4. The MPC8260 does not access the boot
EPROM; it is assumed that the default conÞguration is used upon exiting hard reset.
13Ð15
ISB
Initial internal space base select. DeÞnes the initial value of IMMR[0Ð14] and determines the
base address of the internal memory space.
000 0x0000_0000
001 0x00F0_0000
010 0x0F00_0000
011 0x0FF0_0000
100 0xF000_0000
101 0xF0F0_0000
110 0xFF00_0000
111 0xFFF0_0000
See Section 4.3.2.7, ÒInternal Memory Map Register (IMMR).Ó
base address of the internal memory space.
000 0x0000_0000
001 0x00F0_0000
010 0x0F00_0000
011 0x0FF0_0000
100 0xF000_0000
101 0xF0F0_0000
110 0xFF00_0000
111 0xFFF0_0000
See Section 4.3.2.7, ÒInternal Memory Map Register (IMMR).Ó
16
BMS
Boot memory space. DeÞnes the initial value for BR0[BA]. There are two possible boot memory
regions: HIMEM and LOMEM.
0 0xFE00_0000Ñ0xFFFF_FFFF
1 0x0000_0000Ñ0x01FF_FFFF
See Section 10.3.1, ÒBase Registers (BRx).Ó
regions: HIMEM and LOMEM.
0 0xFE00_0000Ñ0xFFFF_FFFF
1 0x0000_0000Ñ0x01FF_FFFF
See Section 10.3.1, ÒBase Registers (BRx).Ó
17
BBD
Bus busy disable. DeÞnes the initial value of SIUMCR[BBD]. See Section 4.3.2.6, ÒSIU Module
ConÞguration Register (SIUMCR).Ó
ConÞguration Register (SIUMCR).Ó
18Ð19
MMR
Mask masters requests. DeÞnes the initial value of SIUMCR[MMR]. See Section 4.3.2.6, ÒSIU
Module ConÞguration Register (SIUMCR).Ó
Module ConÞguration Register (SIUMCR).Ó
20Ð21
LBPC
Local bus pin conÞguration. DeÞnes the initial value of SIUMCR[LBPC]. See Section 4.3.2.6,
ÒSIU Module ConÞguration Register (SIUMCR).Ó
ÒSIU Module ConÞguration Register (SIUMCR).Ó
22Ð23
APPC
Address parity pin conÞguration. DeÞnes the initial value of SIUMCR[APPC]. See
Section 4.3.2.6, ÒSIU Module ConÞguration Register (SIUMCR).Ó
Section 4.3.2.6, ÒSIU Module ConÞguration Register (SIUMCR).Ó
24Ð25
CS10PC
CS10 pin conÞguration. DeÞnes the initial value of SIUMCR[CS10PC]. See Section 4.3.2.6,
ÒSIU Module ConÞguration Register (SIUMCR).Ó
ÒSIU Module ConÞguration Register (SIUMCR).Ó
26Ð27
Ñ
Reserved, should be cleared.
28Ð31
MODCK_H High-order bits of the MODCK bus, which determine the clock reset conÞguration. See
Chapter 9, ÒClocks and Power Control,Ó for details.
Table 5-7. Hard Reset Configuration Word Field Descriptions (Continued)
Bits
Name
Description