Motorola MPC8260 User Manual
MOTOROLA
Chapter 7. 60x Signals
7-13
Part III. The Hardware Interface
7.2.6.2 Data Bus Busy (DBB)
The data bus busy (DBB) signal is both an input and output signal on the MPC8260
7.2.6.2.1 Data Bus Busy (DBB)ÑOutput
Following are the state meaning and timing comments for the DBB output signal.
Following are the state meaning and timing comments for the DBB output signal.
State Meaning
AssertedÑIndicates that the MPC8260 is the data bus master. The
MPC8260 always assumes data bus mastership if it needs the data
bus and determines a qualiÞed data bus grant (see DBG).
MPC8260 always assumes data bus mastership if it needs the data
bus and determines a qualiÞed data bus grant (see DBG).
NegatedÑIndicates that the MPC8260 is not using the data bus.
Timing Comments
AssertionÑOccurs during the bus clock cycle following a qualiÞed
DBG.
DBG.
NegationÑOccurs for a minimum of one-half bus clock cycle
following the assertion of the Þnal TA following TEA or certain
ARTRY cases.
following the assertion of the Þnal TA following TEA or certain
ARTRY cases.
High ImpedanceÑOccurs after DBB is negated.
7.2.6.2.2 Data Bus Busy (DBB)ÑInput
Following are the state meaning and timing comments for the DBB input signal.
Following are the state meaning and timing comments for the DBB input signal.
State Meaning
AssertedÑIndicates that another device is bus master.
NegatedÑIndicates that the data bus is free (with proper
qualiÞcation, see DBG) for use by the MPC8260.
qualiÞcation, see DBG) for use by the MPC8260.
Timing Comments
AssertionÑMust occur when the MPC8260 must be prevented from
using the data bus.
using the data bus.
NegationÑMay occur whenever the data bus is available.
7.2.7 Data Transfer Signals
Data transfer signals are used in the same way in both internal only and external master
modes. Like the address transfer signals, the data transfer signals are used to transmit data
and to generate and monitor parity for the data transfer. For a detailed description of how
data transfer signals interact, see Section 7.2.7, ÒData Transfer Signals.Ó
modes. Like the address transfer signals, the data transfer signals are used to transmit data
and to generate and monitor parity for the data transfer. For a detailed description of how
data transfer signals interact, see Section 7.2.7, ÒData Transfer Signals.Ó
7.2.7.1 Data Bus (D[0Ð63])
The data bus (D[0Ð63]) states have the same meanings in both internal only mode external
master mode. The data bus consists of 64 signals that are both inputs and outputs on the
MPC8260. Following are the state meaning and timing comments for the data bus.
master mode. The data bus consists of 64 signals that are both inputs and outputs on the
MPC8260. Following are the state meaning and timing comments for the data bus.
State Meaning
The data bus holds 8 byte lanes assigned as shown in Table 7-1.
Timing Comments
The number of times the data bus is driven depends on the transfer
size, port size, and whether the transfer is a single-beat or burst
operation.
size, port size, and whether the transfer is a single-beat or burst
operation.