Motorola MPC8260 User Manual
MOTOROLA
Chapter 8. The 60x Bus
8-1
Chapter 8
The 60x Bus
The 60x Bus
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The 60x bus, which is used by PowerPC processors, provides ßexible support for the on-
chip PowerPC MPC603 processor as well as other internal and external bus devices. The
60x bus supports 32-bit addressing, a 64-bit data bus, and burst operations that transfer as
many as 256 bits of data in a four-beat burst. The 60x data bus can be accessed in 8-, 16-,
32-, and 64-bit data ports. The 60x bus supports accesses of 1, 2, 3, and 4 bytes, aligned or
unaligned, on 4-byte (word) boundaries; it also supports 64-, 128-, 192-, and 256-bit
accesses.
chip PowerPC MPC603 processor as well as other internal and external bus devices. The
60x bus supports 32-bit addressing, a 64-bit data bus, and burst operations that transfer as
many as 256 bits of data in a four-beat burst. The 60x data bus can be accessed in 8-, 16-,
32-, and 64-bit data ports. The 60x bus supports accesses of 1, 2, 3, and 4 bytes, aligned or
unaligned, on 4-byte (word) boundaries; it also supports 64-, 128-, 192-, and 256-bit
accesses.
The address and data buses support synchronous, one-level pipeline transactions. The 60x
bus interface can be conÞgured to support both external and internal masters or internal
masters only.
bus interface can be conÞgured to support both external and internal masters or internal
masters only.
8.1 Terminology
Table 8-1. Terminology
Term
DeÞnition
Atomic
A bus access that attempts to be part of a read-write operation to the same address uninterrupted
by any other access to that address. The MPC8260 initiates the read and write separately, but
signals the memory system that it is attempting an atomic operation. If the operation fails, status is
kept so that MPC8260 can try again.
by any other access to that address. The MPC8260 initiates the read and write separately, but
signals the memory system that it is attempting an atomic operation. If the operation fails, status is
kept so that MPC8260 can try again.
Beat
A single state on the MPC8260 interface that may extend across multiple bus cycles. (An MPC8260
transaction can be composed of multiple address or data beats.)
transaction can be composed of multiple address or data beats.)
Burst
A multiple-beat data transfer whose total size is typically equal to a cache block size (in MPC8260:
32 bytes, or 4 data beats at 8 bytes per beat).
32 bytes, or 4 data beats at 8 bytes per beat).
Cache block
The PowerPC architecture deÞnes the basic unit of coherency as a cache block, which can be
considered the same thing as a cache line.
considered the same thing as a cache line.
Clean
An operation that causes a cache block to be written to memory if modiÞed, and then left in a valid,
unmodiÞed state in the cache.
unmodiÞed state in the cache.
Flush
An operation that causes a cache block to be invalidated in the cache, and its data, if modiÞed, to be
written back to main memory.
written back to main memory.
Kill
An operation that causes a cache block to be invalidated in the cache without writing any modiÞed
data to memory.
data to memory.