Motorola MPC8260 User Manual
MOTOROLA
Chapter 7. 60x Signals
7-17
Part III. The Hardware Interface
NegatedÑIndicates that no bus error was detected.
Timing Comments
AssertionÑMay be asserted while DBB is asserted and for the cycle
after is TA is asserted during a read operation. TEA should be
asserted for one cycle only.
after is TA is asserted during a read operation. TEA should be
asserted for one cycle only.
NegationÑTEA must be negated no later than the negation of DBB.
7.2.8.2.2 Transfer Error Acknowledge (TEA)ÑOutput
Following are the state meaning and timing comments for the TEA output.
Following are the state meaning and timing comments for the TEA output.
State Meaning
AssertedÑIndicates that a bus error has occurred. Assertion of TEA
terminates the transaction in progress; that is, asserting TA is
unnecessary because it is ignored by the target device. An
unsupported memory transaction, such as a direct-store access or a
graphics read or write, causes the assertion of TEA (provided TEA
is enabled and the address transfer matches the MPC8260 memory
map).
terminates the transaction in progress; that is, asserting TA is
unnecessary because it is ignored by the target device. An
unsupported memory transaction, such as a direct-store access or a
graphics read or write, causes the assertion of TEA (provided TEA
is enabled and the address transfer matches the MPC8260 memory
map).
NegatedÑIndicates that no bus error was detected.
Timing Comments
AssertionÑOccurs on the Þrst clock after the bus error is detected.
NegationÑOccurs one clock after assertion.
7.2.8.3 Partial Data Valid Indication (PSDVAL)
The partial data valid indication (PSDVAL) is both an input and output on the MPC8260
7.2.8.3.1 Partial Data Valid (PSDVAL)ÑInput
Following are the state meaning and timing comments for the PSDVAL input signal. Note
that TA asserts with PSDVAL to indicate the termination of the current transfer and for each
complete data beat in burst transactions.
Following are the state meaning and timing comments for the PSDVAL input signal. Note
that TA asserts with PSDVAL to indicate the termination of the current transfer and for each
complete data beat in burst transactions.
State Meaning
AssertedÑIndicates that a beat data transfer completed successfully.
Note that PSDVAL must be asserted for each data beat in a single
beat, port size and burst transaction,. For more information, see
Section 8.5.5, ÒPort Size Data Bus Transfers and PSDVAL
Termination.Ó
Note that PSDVAL must be asserted for each data beat in a single
beat, port size and burst transaction,. For more information, see
Section 8.5.5, ÒPort Size Data Bus Transfers and PSDVAL
Termination.Ó
NegatedÑ(During DBB) indicates that, until PSDVAL is asserted,
the MPC8260 must continue to drive the data for the current write or
must wait to sample the data for reads.
the MPC8260 must continue to drive the data for the current write or
must wait to sample the data for reads.
Timing Comments
AssertionÑMust not occur before AACK for the current transaction
(if the address retry mechanism is to be used to prevent invalid data
from being used by the MPC8260); otherwise, assertion may occur
at any time during the assertion of DBB. The system can withhold
assertion of PSDVAL to indicate that the MPC8260 should insert
wait states to extend the duration of the data beat.
(if the address retry mechanism is to be used to prevent invalid data
from being used by the MPC8260); otherwise, assertion may occur
at any time during the assertion of DBB. The system can withhold
assertion of PSDVAL to indicate that the MPC8260 should insert
wait states to extend the duration of the data beat.
NegationÑMust occur after the bus clock cycle of the Þnal (or only)
data beat of the transfer. For a burst and/or port size transfer, the
data beat of the transfer. For a burst and/or port size transfer, the