Motorola MPC8260 User Manual
MOTOROLA
Chapter 10. Memory Controller
10-13
Part III. The Hardware Interface
Figure 10-5. Partial Data Valid for 32-Bit Port Size Memory, Double-Word Transfer
10.3 Register Descriptions
Table 10-2 lists registers used to control the 60x bus memory controller.
Table 10-2. 60x Bus Memory Controller Registers
Abbreviation
Name
Reference
BR0ÐBR11
Base register banks 0Ð11
OR0ÐOR11]
Option register banks 0Ð11
PSDMR
60x bus SDRAM machine mode register
LSDMR
Local bus SDRAM machine mode register
MAMR
UPMA mode register
MBMR
UPMB mode register
MCMR
UPMC mode register
MDR
Memory data register
MAR
Memory address register
MPTPR
Memory refresh timer prescaler register
PURT
60x bus assigned UPM refresh timer
PSRT
60x bus assigned SDRAM refresh timer
LURT
Local bus assigned UPM refresh timer
LSRT
Local bus assigned SDRAM refresh timer
TESCRx
60x bus error status and control registers
LTESCRx
Local bus error status and control regs
Clock
External
PSDVAL
Internal
TA
Data Bus
Data Bus
(32 msb)
(32 msb)
Upper 4 bytes
Lower 4 bytes
Internal
Data Bus
(32 lsb)
Upper 4 bytes
Lower 4 bytes