Motorola MPC8260 User Manual
10-14
MPC8260 PowerQUICC II UserÕs Manual
MOTOROLA
Part III. The Hardware Interface
10.3.1 Base Registers (BRx)
The base registers (BR0ÐBR11) contain the base address and address types that the
memory controller uses to compare the address bus value with the current address accessed.
Each register also includes a memory attribute and selects the machine for memory
operation handling. Figure 10-6 shows the BRx register format.
memory controller uses to compare the address bus value with the current address accessed.
Each register also includes a memory attribute and selects the machine for memory
operation handling. Figure 10-6 shows the BRx register format.
Table 10-3 describes BRx Þelds.
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Field
BA
Reset
Depends on reset conÞguration sequence. See Section 5.4.1, ÒHard Reset ConÞguration Word.Ó
R/W
R/W
Addr
Bit
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Field
BA
Ñ
PS
DECC
WP
MS
EMEMC
ATOM
DR
V
Reset
0000_0000_0000_0000
1
R/W
Depends on reset conÞguration sequence. See Section 5.4.1, ÒHard Reset ConÞguration Word.Ó
Addr
0x10102 (BR0); 0x1010A (BR1); 0x10112 (BR2); 0x1011A (BR3); 0x10122 (BR4); 0x1012A (BR5); 0x10132
(BR6); 0x1013A (BR7); 0x10142 (BR8); 0x1014A (BR9); 0x10152 (BR10); 0x1015A (BR11)
1
After a system reset, the V bit is set in BR0 and reset in BR[1-11].
Figure 10-6. Base Registers (BRx)
Table 10-3. BRx Field Descriptions
Bits
Name
Description
0Ð16
BA
Base address. The upper 17 bits of each base address register are compared to the address on
the address bus to determine if the bus master is accessing a memory bank controlled by the
memory controller. Used with ORx[BSIZE].
the address bus to determine if the bus master is accessing a memory bank controlled by the
memory controller. Used with ORx[BSIZE].
17Ð18
Ñ
Reserved, should be cleared.
19Ð20
PS
Port size. SpeciÞes the port size of this memory region.
01 8-bit
10 16-bit
11 32-bit
00 64-bit (60x bus only)
01 8-bit
10 16-bit
11 32-bit
00 64-bit (60x bus only)
21Ð22
DECC
Data error correction and checking. SpeciÞes the method for data error checking and correction.
See Section 10.2.3, ÒError Checking and Correction (ECC),Ó and Section 10.2.4, ÒParity
Generation and Checking.Ó
00 Data errors checking disabled
01 Normal parity checking
10 Read-modify-write parity checking
11 ECC correction and checking
See Section 10.2.3, ÒError Checking and Correction (ECC),Ó and Section 10.2.4, ÒParity
Generation and Checking.Ó
00 Data errors checking disabled
01 Normal parity checking
10 Read-modify-write parity checking
11 ECC correction and checking