Motorola MPC8260 User Manual
17-8
MPC8260 PowerQUICC II UserÕs Manual
MOTOROLA
Part IV. Communications Processor Module
17.2.5 Timer Capture Registers (TCR1ÐTCR4)
Each timer capture register (TCR1ÐTCR4), shown in Figure 17-7, is used to latch the value
of the counter according to TMRx[CE].
of the counter according to TMRx[CE].
17.2.6 Timer Counters (TCN1ÐTCN4)
Each timer counter register (TCN1ÐTCN4), shown in Figure 17-8, is an up-counter. A read
cycle to TCNx yields the current value of the timer but does not affect the counting
operation. A write cycle to TCNx sets the register to the written value, thus causing its
corresponding prescaler, TMRx[PS], to be reset.
cycle to TCNx yields the current value of the timer but does not affect the counting
operation. A write cycle to TCNx sets the register to the written value, thus causing its
corresponding prescaler, TMRx[PS], to be reset.
Note that the counter registers may not be updated correctly if a write is made while the
timer is not running. Use TRRx to deÞne the preferred count value.
timer is not running. Use TRRx to deÞne the preferred count value.
17.2.7 Timer Event Registers (TER1ÐTER4)
Each timer event register (TERx), shown in Figure 17-9, reports events recognized by the
timers. When an output reference event is recognized, the timer sets TERx[REF] regardless
of the corresponding TMRx[ORI]. The capture event is set only if it is enabled by
TMRx[CE]. TER1ÐTER4 can be read at any time.
timers. When an output reference event is recognized, the timer sets TERx[REF] regardless
of the corresponding TMRx[ORI]. The capture event is set only if it is enabled by
TMRx[CE]. TER1ÐTER4 can be read at any time.
Writing ones clears event bits; writing zeros has no effect. Both event bits must be cleared
before the timer negates the interrupt.
before the timer negates the interrupt.
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Field
Latched counter value
Reset
0x0000
R/W
R/W
Addr
Figure 17-7. Timer Capture Registers (TCR1ÐTCR4)
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Field
Up counter
Reset
0x0000
R/W
R/W
Addr
Figure 17-8. Timer Counter Registers (TCN1ÐTCN4)
Bits
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Field
Ñ
REF
CAP
Reset
0x0000
Addr
Figure 17-9. Timer Event Registers (TER1ÐTER4)