Motorola MPC8260 User Manual
MOTOROLA
Chapter 18. SDMA Channels and IDMA Emulation
18-9
Part IV. Communications Processor Module
Because at least one of the transfer sizes (STS or DTS) equals SS_MAX, every DREQ
assertion causes one transfer to the smaller (in STS/DTS terms) bus. If STS = DTS,
asserting DREQ triggers one read transfer automatically followed by one write transfer.
assertion causes one transfer to the smaller (in STS/DTS terms) bus. If STS = DTS,
asserting DREQ triggers one read transfer automatically followed by one write transfer.
NOTE
External request mode does not support external DONE
signaling from a device and DACK signaling from an IDMA
channel.
signaling from a device and DACK signaling from an IDMA
channel.
18.5.1.2 Normal Mode
When external request mode is not selected (DCM[ERM] = 0), the IDMA channel operates
automatically, ignoring DREQ.
automatically, ignoring DREQ.
18.5.2 Memory to/from Peripheral Transfers
Working with peripheral devices requires the external signals DONE, DREQ, DACK to
control the data transfer using the following rules:
control the data transfer using the following rules:
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The peripheral sets a request for data to be read-from/write-to by asserting DREQ
as conÞgured, falling or rising edge sensitive.
as conÞgured, falling or rising edge sensitive.
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The peripheral transfers/samples the data when DACK is asserted.
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The peripheral asserts DONE to stop the current transfer.
¥
The peripheral terminates the current transfer when DONE is asserted, combined
with DACK, by the IDMA.
with DACK, by the IDMA.
Peripherals are usually accessed with Þxed port-size transfers. The transfer sizes (STS/
DTS) related to the peripheral must be programmed to its port size; thus, every access to a
peripheral yields a single bus transaction. The maximum peripheral port size is (bus_width
- 8) bytes and also should evenly divide the buffer length, BD[Data Length].
DTS) related to the peripheral must be programmed to its port size; thus, every access to a
peripheral yields a single bus transaction. The maximum peripheral port size is (bus_width
- 8) bytes and also should evenly divide the buffer length, BD[Data Length].
A peripheral can also be conÞgured to accept a burst per DREQ assertion. In this case, the
transfer size parameter should be initialized to 32, and the accesses are made in bursts. See
Table 18-8.
transfer size parameter should be initialized to 32, and the accesses are made in bursts. See
Table 18-8.
A peripheral can be accessed at a Þxed address location or at incremental addresses. Setting
DCM[SINC, DINC] in the DMA channel mode register causes the address to be
incremented before the next transfer; see Section 18.8.2.1, ÒDMA Channel Mode (DCM).Ó
This allows the IDMA to access a FIFO buffer the same way it does peripherals.
DCM[SINC, DINC] in the DMA channel mode register causes the address to be
incremented before the next transfer; see Section 18.8.2.1, ÒDMA Channel Mode (DCM).Ó
This allows the IDMA to access a FIFO buffer the same way it does peripherals.
DCM[S/D] determines whether the peripheral is the source or destination.