Motorola MPC8260 User Manual
18-10
MPC8260 PowerQUICC II UserÕs Manual
MOTOROLA
Part IV. Communications Processor Module
Data can be transferred between a peripheral and memory in single- or dual-address
accesses:
accesses:
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For dual-address accesses, the data is read from the source, temporarily stored in the
IDMA transfer buffer in the dual-port RAM, and then written to the destination.
IDMA transfer buffer in the dual-port RAM, and then written to the destination.
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For single-address accesses (ßy-by mode), the data is transferred directly between
memory and the peripheral. Memory responds to the address phase, while the
peripheral ignores it and responds to DACK assertions.
memory and the peripheral. Memory responds to the address phase, while the
peripheral ignores it and responds to DACK assertions.
Any IDMA access to a peripheral uses the highest arbitration priority allowed for the DMA,
providing faster bus access by bypassing other pending DMA requests.
providing faster bus access by bypassing other pending DMA requests.
18.5.2.1 Dual-Address Transfers
The following sections discuss various dual-address transfers.
18.5.2.1.1 Peripheral to Memory
Dual-address peripheral-to-memory data transfers are similar to memory-to-memory
transfers using the three-phase algorithm; see Section 18.5.1, ÒMemory-to-Memory
Transfers.Ó When a peripheral asserts DREQ, data is loaded from the peripheral in port-size
units to the internal transfer buffer. When the transfer buffer reaches the steady-state level,
it is automatically written to the memory destination in one transfer. The source transfer
size (STS) is initialized to the peripheral port size, and the destination transfer size (DTS)
is initialized to SS_MAX.
Dual-address peripheral-to-memory data transfers are similar to memory-to-memory
transfers using the three-phase algorithm; see Section 18.5.1, ÒMemory-to-Memory
Transfers.Ó When a peripheral asserts DREQ, data is loaded from the peripheral in port-size
units to the internal transfer buffer. When the transfer buffer reaches the steady-state level,
it is automatically written to the memory destination in one transfer. The source transfer
size (STS) is initialized to the peripheral port size, and the destination transfer size (DTS)
is initialized to SS_MAX.
External requests must be enabled (DCM[ERM] = 1) for dual-address peripheral-to-
memory transfers. If DONE is asserted externally by the peripheral or if a
memory transfers. If DONE is asserted externally by the peripheral or if a
STOP
_
IDMA
command is issued, the current transfer stops. All data in the internal transfer buffer is
written to memory in one transfer before its BD is closed, and the IDSR[EDN] or
IDSR[SC] event bits are set; see Section 18.8.4, ÒIDMA Event Register (IDSR) and Mask
Register (IDMR).Ó
written to memory in one transfer before its BD is closed, and the IDSR[EDN] or
IDSR[SC] event bits are set; see Section 18.8.4, ÒIDMA Event Register (IDSR) and Mask
Register (IDMR).Ó
When the peripheral controls a transfer of unknown length, initialize a large enough buffer
so that the peripheral will most likely assert DONE before overßowing the buffer. When
DONE is asserted, the BD is closed and interrupts are generated (if enabled). The next
DREQ assertion opens the next BD if DCM[DT] is set; see Section 18.8.2.1, ÒDMA
Channel Mode (DCM).Ó
so that the peripheral will most likely assert DONE before overßowing the buffer. When
DONE is asserted, the BD is closed and interrupts are generated (if enabled). The next
DREQ assertion opens the next BD if DCM[DT] is set; see Section 18.8.2.1, ÒDMA
Channel Mode (DCM).Ó
18.5.2.1.2 Memory to Peripheral
Dual-address memory-to-peripheral data transfers are similar to memory-to-memory
transfers using the three-phase algorithm; see Section 18.5.1, ÒMemory-to-Memory
Transfers.Ó STS is initialized to SS_MAX and DTS is initialized to the peripheral port size.
The Þrst DREQ peripheral assertion triggers a read of SS_MAX (or more in the Þrst phase)
bytes from the memory into the internal transfer buffer, automatically followed by a write
of DTS bytes to the peripheral. Subsequent DREQ assertions trigger writes to the
Dual-address memory-to-peripheral data transfers are similar to memory-to-memory
transfers using the three-phase algorithm; see Section 18.5.1, ÒMemory-to-Memory
Transfers.Ó STS is initialized to SS_MAX and DTS is initialized to the peripheral port size.
The Þrst DREQ peripheral assertion triggers a read of SS_MAX (or more in the Þrst phase)
bytes from the memory into the internal transfer buffer, automatically followed by a write
of DTS bytes to the peripheral. Subsequent DREQ assertions trigger writes to the