Motorola MPC8260 User Manual
MOTOROLA
Chapter 18. SDMA Channels and IDMA Emulation
18-13
Part IV. Communications Processor Module
and DMA done (DONE[1Ð4]). DREQx may also be used to control the transfer pace of
memory-to-memory transfers.
memory-to-memory transfers.
¥
DREQx is the external DMA request signal.
¥
DACKx is the DMA acknowledge.
¥
DONEx marks the end of an IDMA transfer.
The IDMA signals are multiplexed with other internal controller signals at the parallel I/O
ports. To enable the IDMA signals, the corresponding bits in the parallel I/O registers
should be set. See Chapter 35, ÒParallel I/O Ports.Ó
ports. To enable the IDMA signals, the corresponding bits in the parallel I/O registers
should be set. See Chapter 35, ÒParallel I/O Ports.Ó
18.7.1 DREQx and DACKx
When the peripheral requires IDMA service, it asserts DREQx and the MPC8260 begins
the IDMA process. When the IDMA service is in progress, DACKx is asserted during
accesses to the peripheral. A peripheral must validate the transfer by asserting TA or signal
an error by asserting TEA.
the IDMA process. When the IDMA service is in progress, DACKx is asserted during
accesses to the peripheral. A peripheral must validate the transfer by asserting TA or signal
an error by asserting TEA.
DREQx may be conÞgured as either edge- or level-sensitive by programming the
RCCR[DRxM]. When DREQx is conÞgured as edge-sensitive, RCCR[EDMx] controls
whether the request is generated on the rising or falling edge; see Section 13.3.6, ÒRISC
Controller ConÞguration Register (RCCR).Ó
RCCR[DRxM]. When DREQx is conÞgured as edge-sensitive, RCCR[EDMx] controls
whether the request is generated on the rising or falling edge; see Section 13.3.6, ÒRISC
Controller ConÞguration Register (RCCR).Ó
DREQx is sampled at each rising edge of the clock to determine when a valid request is
asserted by the device.
asserted by the device.
18.7.1.1 Level-Sensitive Mode
For external devices requiring very high data transfer rates, level-sensitive mode allows the
IDMA to use a maximum bandwidth to service the device. The device requests service by
asserting DREQx and leaving it asserted as long as it needs service. This mode is selected
by setting the corresponding RCCR[DRxM].
IDMA to use a maximum bandwidth to service the device. The device requests service by
asserting DREQx and leaving it asserted as long as it needs service. This mode is selected
by setting the corresponding RCCR[DRxM].
The IDMA asserts DACK each time it issues a bus transaction to either read or write the
peripheral. The peripheral must use TA and TEA for data validation. DACK is the
acknowledgment of the original burst request given on DREQx. DREQx should be negated
during the DACK active period to ensure that no further transactions are performed.
peripheral. The peripheral must use TA and TEA for data validation. DACK is the
acknowledgment of the original burst request given on DREQx. DREQx should be negated
during the DACK active period to ensure that no further transactions are performed.
18.7.1.2 Edge-Sensitive Mode
For external devices that generate a pulsed signal for each operand to be transferred, edge-
sensitive mode should be used. In edge-sensitive mode, the IDMA controller moves one
operand for each falling/rising (as conÞgured by RCCR[EDMx]) edge of DREQx. This
mode is selected by clearing the corresponding RCCR[DRxM] and programming the
corresponding RCCR[EDMx] to the proper edge.
sensitive mode should be used. In edge-sensitive mode, the IDMA controller moves one
operand for each falling/rising (as conÞgured by RCCR[EDMx]) edge of DREQx. This
mode is selected by clearing the corresponding RCCR[DRxM] and programming the
corresponding RCCR[EDMx] to the proper edge.
When the IDMA controller detects a valid edge on DREQx, a request becomes pending and
remains pending until it is serviced by the IDMA. Subsequent changes on DREQx are
remains pending until it is serviced by the IDMA. Subsequent changes on DREQx are