Motorola MPC8260 User Manual
18-14
MPC8260 PowerQUICC II UserÕs Manual
MOTOROLA
Part IV. Communications Processor Module
ignored until the request begins to be serviced. The servicing of the request results in one
operand being transferred. Each time the IDMA issues a bus transaction to either read or
write the device, the IDMA asserts DACK. The device must use TA and TEA for data
validation. Thus, DACK is the acknowledgment of the original transaction request given on
DREQx.
operand being transferred. Each time the IDMA issues a bus transaction to either read or
write the device, the IDMA asserts DACK. The device must use TA and TEA for data
validation. Thus, DACK is the acknowledgment of the original transaction request given on
DREQx.
18.7.2 DONEx
This bidirectional open-drain signal is used to indicate the last IDMA transfer. DONE can
be an output of the IDMA in the source or destination bus transaction if the transfer count
is exhausted. This function is controlled by BD[SDN, DDN].
be an output of the IDMA in the source or destination bus transaction if the transfer count
is exhausted. This function is controlled by BD[SDN, DDN].
DONE can also operate as an input. When operating in external request modes, DONE may
be used as an input to the IDMA controller to indicate that the device being serviced
requires no more transfers. In that case, the transfer is terminated, the current BD is closed,
and an interrupt is generated (if enabled).
be used as an input to the IDMA controller to indicate that the device being serviced
requires no more transfers. In that case, the transfer is terminated, the current BD is closed,
and an interrupt is generated (if enabled).
NOTE
DONE is ignored if it is asserted externally during internal
request mode (DCM[ERM] = 0).
request mode (DCM[ERM] = 0).
DONE must not be asserted externally during memory-to-
memory transfers if external request mode is enabled
(DCM[ERM] = 1).
memory transfers if external request mode is enabled
(DCM[ERM] = 1).
18.8 IDMA Operation
Every IDMA operation involves the following stepsÑIDMA channel initialization, data
transfer, and block termination.
transfer, and block termination.
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During initialization, the core initializes the IDMA_BASE register in the internal
parameter RAM to point to the IDMA-speciÞc table in RAM. This table contains
control information for the IDMA operation. In addition the core initializes the
parallel I/O registers to enable IDMA external signals, if needed, and other registers
related to the channel priority and operation modes; see Section 18.11,
ÒProgramming the Parallel I/O Registers.Ó The core initiates the IDMA BDs to point
to the data for the transfer and/or a free space for data to be transferred to, and starts
the transfer by issuing the
parameter RAM to point to the IDMA-speciÞc table in RAM. This table contains
control information for the IDMA operation. In addition the core initializes the
parallel I/O registers to enable IDMA external signals, if needed, and other registers
related to the channel priority and operation modes; see Section 18.11,
ÒProgramming the Parallel I/O Registers.Ó The core initiates the IDMA BDs to point
to the data for the transfer and/or a free space for data to be transferred to, and starts
the transfer by issuing the
START
_
IDMA
command.
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During data transfer, the IDMA accepts requests for data transfers and provides
addressing and bus control for the transfers.
addressing and bus control for the transfers.
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Termination occurs when the IDMA operation completes or the peripheral asserts
DONE externally. The core can initiate termination by using the
DONE externally. The core can initiate termination by using the
STOP
_
IDMA
command. The IDMA can interrupt the core if interrupts are enabled to signal for
operation termination and other events related to the data transfer.
operation termination and other events related to the data transfer.
The IDMA uses a data structure, which, as with serial controller BDs, allows ßexible data