Motorola MPC8260 User Manual

29-15

MOTOROLA

The external CAM Þelds are described in Table 29-2

The address compression mechanism uses two levels of address translation to help
minimize the memory space needed to cover the available address range. The Þrst level of
translation (VP-level) uses a look-up table based on the 4-bit PHY address and the 12-bit
virtual path identiÞer; the second level (VC-level) uses the 16-bit virtual channel identiÞer.
If there is no match during address compression, the cell is considered a misinserted cell.

During the VP-level translation, VP_MASK in the ATM parameter RAM compresses an
incoming cellÕs PHY address and VPI to create an index into the VP-level table. The VP-
level table entry consists of another mask (VC_MASK) and a pointer to one of the VC-level
tables (VCOFFSET). Note that the VP table should reside in the dual-port RAM.

In the VC-level translation, the VCI is compressed with the VC_MASK to generate a
pointer to the VC-level table entry containing the received cellÕs channel code. The VC table
should reside in external memory.

Figure 29-5 shows an example of address compression. 

PHY Addr 

In multiple PHY mode, this Þeld contains the 4 least-signiÞcant bits of the current channelÕs physical 
address. Because this CAM comparison Þeld is limited to 4 bits, two CAM devices are needed if using 
more than 16 PHYs.The msb of the PHY address lines (bit 4) selects between the two devices. If the 
msb is zero, the CP accesses the CAM whose address is written in the EXT_CAM_BASE parameter in 
the parameter RAM; if the msb is set, the CP uses EXT_CAM1_BASE. See Section 15.4.1, ÒCMX 
UTOPIA Address Register (CMXUAR).Ó
In single PHY mode, clear this Þeld.

GFC+VPI,
VCI

The GFC, VPI, and VCI of the current channel.

Ch Code

Pointer to internal or external connection table.

Ñ

Reserved, should be cleared.

MS

Match status.
0 Match was found.
1 Match was not found.