Motorola MPC8260 User Manual
29-77
MPC8260 PowerQUICC II UserÕs Manual
MOTOROLA
Part IV. Communications Processor Module
29.10.5.10 AAL0 TxBDs
Figure 29-52 shows AAL0 TxBDs. Note that the data length Þeld is calculated internally as
52 bytes, plus the extra header length (deÞned in FPSMR[TEHS]) when in UDC mode.
52 bytes, plus the extra header length (deÞned in FPSMR[TEHS]) when in UDC mode.
Table 29-40 describes AAL0 TxBD Þelds.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Offset + 0x00
R
Ñ
W
I
Ñ
CM
Ñ
OAM
Ñ
Offset + 0x02
Ñ
Offset + 0x04
Tx Data Buffer Pointer (TXDBPTR)
Offset + 0x06
Figure 29-52. AAL0 TxBDs
Table 29-40. AAL0 TxBD Field Descriptions
Offset
Bits
Name
Description
0x00
0
R
Ready
0 The buffer is not ready for transmission. The user can manipulate this BD or its
0 The buffer is not ready for transmission. The user can manipulate this BD or its
buffer. The CP clears R after the buffer has been sent or after an error occurs.
1 The buffer that the user prepared for transmission has not been sent or is being
sent. No Þelds of this BD may be written by the user once R is set.
1
Ñ
Reserved, should be cleared.
2
W
Wrap (Þnal BD in table)
0 Not the last BD in the TxBD table.
1 Last BD in the TxBD table. After this buffer is used, the CP sends outgoing data
0 Not the last BD in the TxBD table.
1 Last BD in the TxBD table. After this buffer is used, the CP sends outgoing data
from the Þrst BD in the table (the BD pointed to by the channelÕs
TCT[TBD_BASE]). The number of TxBDs in this table is determined by the W bit.
The current table is constrained to 64 Kbytes.
TCT[TBD_BASE]). The number of TxBDs in this table is determined by the W bit.
The current table is constrained to 64 Kbytes.
3
I
Interrupt
0 No interrupt is generated after this buffer has been serviced.
1 A Tx buffer event is sent to the interrupt queue after this buffer is serviced.
0 No interrupt is generated after this buffer has been serviced.
1 A Tx buffer event is sent to the interrupt queue after this buffer is serviced.
FCCE[GINTx] is set when the INT_CNT counter reaches the global interrupt
threshold.
threshold.
4Ð5
Ñ
Reserved, should be cleared.
6
CM
Continuous mode
0 Normal operation.
1 The CP does not clear the ready bit after this BD is closed, allowing the associated
0 Normal operation.
1 The CP does not clear the ready bit after this BD is closed, allowing the associated
buffer to be retransmitted automatically when the CP next accesses this BD.
7Ð10
Ñ
Reserved, should be cleared.
11
OAM
Operation and maintenance cell. If OAM is set, the current AAL0 buffer contains an
F5 or F4 OAM cell. Performance monitoring calculations are not done on OAM cells.
F5 or F4 OAM cell. Performance monitoring calculations are not done on OAM cells.
11Ð15
Ñ
Reserved, should be cleared.
0x02
Ñ
Ñ
Reserved, should be cleared.
0x04
Ñ
TXDBPTR Tx data buffer pointer. Points to the address of the associated buffer, which may or
may not be 8-byte-aligned. The buffer may reside in either internal or external
memory. This value is not modiÞed by the CP.
memory. This value is not modiÞed by the CP.