Motorola MPC8260 User Manual
29-79
MPC8260 PowerQUICC II UserÕs Manual
MOTOROLA
Part IV. Communications Processor Module
29.11 ATM Exceptions
The ATM controller interrupt handling involves two principal data structures: FCCEs (FCC
event registers) and circular interrupt queues.
event registers) and circular interrupt queues.
Four priority interrupt queues are available. By programming RCT[INTQ] and
TCT[INTQ], the user determines which queue receives the interrupt. Channel Rx buffer, Rx
frame, or Tx buffer events can be masked by clearing interrupt mask bits in RCT and TCT.
TCT[INTQ], the user determines which queue receives the interrupt. Channel Rx buffer, Rx
frame, or Tx buffer events can be masked by clearing interrupt mask bits in RCT and TCT.
After an interrupt request, the host reads FCCE. If FCCE[GINTx] = 1, at least one entry
was added to one of the interrupt queues. After clearing FCCE[GINTx], the host processes
the valid interrupt queue entries and clears each entryÕs valid bit. The host follows this
procedure until it reaches an entry with V = 0. See Section 29.11.2, ÒInterrupt Queue
Entry.Ó
was added to one of the interrupt queues. After clearing FCCE[GINTx], the host processes
the valid interrupt queue entries and clears each entryÕs valid bit. The host follows this
procedure until it reaches an entry with V = 0. See Section 29.11.2, ÒInterrupt Queue
Entry.Ó
The host controls the number of interrupts sent to the core using a counter in the interrupt
queueÕs parameter table; see Section 29.11.3. For each event sent to an interrupt queue, a
counter (that has been initialized to a threshold number of interrupts) is decremented. When
the counter reaches zero, the global interrupt, FCCE[GINTx], is set.
queueÕs parameter table; see Section 29.11.3. For each event sent to an interrupt queue, a
counter (that has been initialized to a threshold number of interrupts) is decremented. When
the counter reaches zero, the global interrupt, FCCE[GINTx], is set.
29.11.1 Interrupt Queues
Interrupt queues are located in external memory. The parameters of each queue are stored
in a table. See Section 29.11.3, ÒInterrupt Queue Parameter Tables.Ó
in a table. See Section 29.11.3, ÒInterrupt Queue Parameter Tables.Ó
When an interrupt occurs, the CP writes a new entry to the interrupt queue, the V bit is set,
and the queue pointer (INTQ_PTR) is incremented. Once the CP uses an entry with W = 1,
it returns to the Þrst entry in the queue. If the CP tries to overwrite a valid entry (V = 1), an
overßow condition occurs and the queueÕs overßow ßag, FCCE[INTOx], is set.
and the queue pointer (INTQ_PTR) is incremented. Once the CP uses an entry with W = 1,
it returns to the Þrst entry in the queue. If the CP tries to overwrite a valid entry (V = 1), an
overßow condition occurs and the queueÕs overßow ßag, FCCE[INTOx], is set.
Table 29-41. UNI Statistics Table
Offset
1
1
Offset from UNI_STATT_BASE+PHY#
´ 8
Name
Width
Description
0x00
UTOPIAE
Hword
Counts cells dropped as a result of UTOPIA parity error or state machine
errors (short or long cells).
errors (short or long cells).
0x02
MIC_COUNT
Hword
Counts misinserted cells dropped as a result of address look-up failure.
0x04
CRC10E_COUNT Hword
Counts cells dropped as a result of CRC10 failure. AAL5-ABR only.
0x06
Ñ
Hword
Reserved, should be cleared.