Motorola MPC8260 User Manual
29-87
MPC8260 PowerQUICC II UserÕs Manual
MOTOROLA
Part IV. Communications Processor Module
29.13.3 ATM Event Register (FCCE)/Mask Register (FCCM)
The FCCE register is the ATM controller event register when the FCC operates in ATM
mode. When it recognizes an event, the ATM controller sets the corresponding FCCE bit.
Interrupts generated by this register can be masked in FCCM. FCCE is memory-mapped
and can be read at any time. Bits are cleared by writing ones to them; writing zeros has no
effect. Unmasked bits must be cleared before the CP clears the internal interrupt request.
mode. When it recognizes an event, the ATM controller sets the corresponding FCCE bit.
Interrupts generated by this register can be masked in FCCM. FCCE is memory-mapped
and can be read at any time. Bits are cleared by writing ones to them; writing zeros has no
effect. Unmasked bits must be cleared before the CP clears the internal interrupt request.
FCCM is the ATM controller mask register. It is a 16-bit read/write register with the same
bit format as FCCE. If an FCCM bit is set, the corresponding interrupt is enabled in FCCE.
If it is cleared, the corresponding interrupt is masked. FCCM is cleared at reset.
bit format as FCCE. If an FCCM bit is set, the corresponding interrupt is enabled in FCCE.
If it is cleared, the corresponding interrupt is masked. FCCM is cleared at reset.
21
RxP
Receive parity check.
0 Check Rx parity line.
1 Do not check Rx parity line.
0 Check Rx parity line.
1 Do not check Rx parity line.
22
TUMP
Transmit UTOPIA multiple PHY mode
0 Transmit UTOPIA single PHY mode is selected.
1 Transmit UTOPIA multiple PHY mode is selected.
0 Transmit UTOPIA single PHY mode is selected.
1 Transmit UTOPIA multiple PHY mode is selected.
23
Ñ
Reserved, should be cleared.
24
TSIZE
Transmit UTOPIA data bus size
0 UTOPIA 8-bit data bus size.
1 UTOPIA 16-bit data bus size.
0 UTOPIA 8-bit data bus size.
1 UTOPIA 16-bit data bus size.
25
RSIZE
Receive UTOPIA data bus size
0 UTOPIA 8-bit data bus size.
1 UTOPIA 16-bit data bus size.
0 UTOPIA 8-bit data bus size.
1 UTOPIA 16-bit data bus size.
26
UPRM
UTOPIA priority mode.
0 Round robin. Polling is done from PHY zero to the PHY speciÞed in LAST PHY. When a
0 Round robin. Polling is done from PHY zero to the PHY speciÞed in LAST PHY. When a
PHY is selected, the UTOPIA interface continues to poll the next PHY in order.
1 Fixed priority. Polling is done from PHY zero to the PHY speciÞed in LAST PHY. When a
PHY is selected, the UTOPIA interface continues to poll from PHY zero.
27
UPLM
UTOPIA polling mode.
0 Multiplex polling. Polling is done using RxAdd[0Ð4] and Clav[0]. Selection is done using
0 Multiplex polling. Polling is done using RxAdd[0Ð4] and Clav[0]. Selection is done using
RxAdd[0Ð4]. Up to 31 PHYs can be polled.
1 Direct polling. Polling is done using Clav[0Ð3]. Selection is done using RxAdd[0Ð2]. Up to 4
PHYs can be polled.
28
RUMP
Receive UTOPIA multiple PHY mode.
0 Receive UTOPIA single PHY mode is selected.
1 Receive UTOPIA multiple PHY mode is selected.
0 Receive UTOPIA single PHY mode is selected.
1 Receive UTOPIA multiple PHY mode is selected.
29
HECI
HEC included. Used in UDC mode only.
0 HEC octet is not included when UDC mode is enabled.
1 HEC octet is included when UDC mode is enabled.
0 HEC octet is not included when UDC mode is enabled.
1 HEC octet is included when UDC mode is enabled.
30Ð31
Ñ
Reserved, should be cleared.
Table 29-47. FCC ATM Mode Register (FPSMR) (Continued)
Bits
Name Description