Motorola MPC8260 User Manual

29-88

MOTOROLA

29.13.4  FCC Transmit Internal Rate Registers (FTIRRx)

The Þrst four PHY devices (address 00-03) have their own FCC transmit internal rate
registers (FTIRRx_PHY0ÐFTIRRx_PHY3) for use in transmit internal rate mode. In this
mode, the total transmission rate is determined by FCC internal rate timers. FTIRRx, shown
in Figure 29-61, includes the initial value of the internal rate timer. The source clock of the
internal rate timers is supplied by one of four baud-rate generators selected in CMXUAR;
see Section 15.4.1, ÒCMX UTOPIA Address Register (CMXUAR).Ó Note that in slave
mode, FTIRRx_PHY0 is used regardless of the slave PHY address.

Bits

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Field

Ñ

TIRU GRLI GBPB GINT3 GINT2 GINT1 GINT0 INTO3 INTO2 INTO1 INTO0

Reset

0000_0000_0000_0000

R/W

R/W

Address

0Ð4

Ñ

Reserved, should be cleared.

5

TIRU

Transmit internal rate underrun. A transmit internal rate counter expired and a cell was not sent 
because the transmit FIFO was empty. TIRU may be set only when using transmit internal rate mode; 
see Section 29.13.4, ÒFCC Transmit Internal Rate Registers (FTIRRx).Ó

6

GRLI

Global red-line interrupt. GRLI is set when a free buffer poolÕs RLI ßag is set. The RLI ßag is also set 
in the free buffer poolÕs parameter table.

7

GBPB Global buffer pool busy interrupt. GBPB is set when a free buffer poolÕs BUSY ßag is set. The BUSY 

ßag is also set in the free buffer poolÕs parameter table.

8Ð11

GINTx Global interrupt. Set when an event is sent to the corresponding interrupt queue. See Section 29.11, 

ÒATM Exceptions.Ó

12Ð
15

INTOx Interrupt queue overßow. Set when an overßow condition occurs in the corresponding interrupt 

queue. This occurs when the CP attempts to overwrite a valid interrupt entry. See Section 29.11.1, 
ÒInterrupt Queues.Ó