Motorola MPC8260 User Manual

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MOTOROLA
Chapter 32.  FCC Transparent Controller  
32-3
Part IV.  Communications Processor Module
32.3.1  In-Line Synchronization Pattern
The transparent channel can be programmed to transmit and receive a synchronization
pattern if GFMR[SYNL] 
The pattern is deÞned in the FDSR; see Section 28.4, ÒFCC Data Synchronization Registers
(FDSRx).
Ó GFMR[SYNL] deÞnes the SYNC pattern length. The synchronization pattern
is shown in Figure 32-1.
The receiver synchronizes on the synchronization pattern located in the FDSR. For
instance, if an 8-bit SYNC is selected, reception begins as soon as these eight bits are
received, beginning with the Þrst bit following the 8-bit SYNC. This effectively links the
transmitter synchronization to the receiver synchronization.
32.3.2  External Synchronization Signals
If GFMR[SYNL] = 00, an external signal is used to begin the sequence. CTS is used for the
transmitter and CD is used for the receiver; these signals share the following sampling
options. 
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The pulse option determines whether CD or CTS need to only be asserted once to 
begin reception/transmission or whether they must be asserted and stay that way for 
the duration of the transparent frame. This is controlled by the CDP and CTSP bits 
of the GFMR. If the user expects a continuous stream of data without interruption, 
then the pulse operation should be used. However, if the user is trying to identify 
frames of transparent data, the envelope mode of the these signals should be used.
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The sampling option determines the delay between CD and CTS being asserted and 
the resulting action by the FCC. These signals can be assumed to be asynchronous 
to the data and then internally synchronized by the FCC, or they can be assumed to 
be synchronous to the data giving faster operation. This option allows the RTS of one 
FCC to be connected to the CD of another FCC (on another MPC8260) and to have 
the data synchronized and bit aligned. It is also an option to link the transmitter 
synchronization to the receiver synchronization.
Bits
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Field
8-Bit Sync Pattern
Ñ
Field
16-Bit Sync Pattern
Figure 32-1. In-Line Synchronization Pattern