Motorola MPC8260 User Manual

MOTOROLA

Chapter 35.  Parallel I/O Ports  

35-19

The port C lines associated with CDx and CTSx have a mode of operation where the pin
can be internally connected to the SCC/FCC but can also generate interrupts. Port C still
detects changes on the CTS and CD pins and asserts the corresponding interrupt request,
but the SCC/FCC simultaneously uses CTS and/or CD to automatically control operation.
This lets the user fully implement protocols V.24, X.21, and X.21 bis (with the assistance
of other general-purpose I/O lines). 

To conÞgure a port C pin as a CTS or CD pin that connects to the SCC/FCC and generates
interrupts, these steps should be followed:

1. Write the corresponding PPARC bit with a 1 and PSORC bit with 0.

2. Write the corresponding PDIRC bit with a zero.

3. Set the SIEXR bit (in the interrupt controller) to determine which edges cause 

interrupts.

PD8

UTOPIA

GND

PD7

GND

MPHY, master, 

multiplexed polling

MPHY, master, 

multiplexed polling

MPHY, slave, 

multiplexed polling

MPHY, master, direct 

polling

MPHY, slave, 

multiplexed polling

GND

PD6

UTOPIA 16

PD5

UTOPIA 16

Inout

(secondary option)

V

DD

PD4

(secondary option)

GND

(secondary option)

GND

1

MPHY address pins 3 and 4 (master mode) can come from FCC2, depending on CMXUAR programming. (See 

Section 15.4.1, ÒCMX UTOPIA Address Register (CMXUAR).Ó)

2

MPHY address pins 0Ð4 (slave mode) can come from FCC2, depending on CMXUAR programming. (See 

Section 15.4.1, ÒCMX UTOPIA Address Register (CMXUAR).Ó)

3

Available only when the primary option for this function is not used.

PDIRD = 0 (Input, or