Motorola DSP56012 User Manual

Synchronization is a common problem when two asynchronous systems are 
connected, and careful synchronization is required when reading multiple-bit 
registers that are written by another asynchronous system. The considerations for 
proper operation on the DSP CPU side are discussed in the following paragraphs, 
and considerations for the host processor side are discussed in 

 

.

The DMA, HF1, HF0, HCP, HTDE, and HRDF status bits are set or cleared by the 
host processor side of the interface. These bits are individually synchronized to the 
DSP clock.

The only system problem with reading status occurs if HF1 and HF0 are 
encoded as a pair because each of their four combinations (00, 01, 10, and 11) 
has significance. There is a small possibility that the DSP will read the status 
bits during the transition and receive “01” or “10” instead of “11”. The 
solution to this potential problem is to read the bits twice for consensus (see 

information).

The host can access the HI asynchronously by using either polling techniques or 
interrupt-based techniques. Separate transmit and receive data registers are 
double-buffered to allow the DSP CPU and host processor to transfer data efficiently 
at high speed. The HI contains a rudimentary DMA controller, which makes 
generating addresses (HOA[2:0]) for the TX/RX registers in the HI unnecessary.

The HI appears to the host processor as a memory-mapped peripheral occupying 
eight bytes in the host processor address space (see 

). These registers can 

be viewed as the Interrupt Control Register (ICR), the Interrupt Status Register (ISR), 
three Receive/Transmit data registers (RXH/TXH, RXM/TXM, and RXL/TXL), and 
two vector registers, the Interrupt Vector Register (IVR) and the Command Vector 
Register (CVR). The CVR is a special command register that is used by the host 
processor to issue commands to the DSP. These registers can be accessed only by the 
host processor; they can not be accessed by the DSP. Host processors can use 
standard host processor instructions (e.g., byte move) and addressing modes to 
communicate with the HI registers. The HI registers are addressed so that 8-bit 
MC6801-type host processors can use 16-bit load (LDD) and store (STD) instructions 
for data transfers. The 16-bit MC68000/MC68010 host processor can address the HI 
using the special MOVEP instruction for word (16-bit) or long-word (32-bit)