Motorola DSP56012 User Manual

The Interrupt Control Register (ICR) is an 8-bit read/write control register used by 
the host processor to control the HI interrupts and flags. The ICR cannot be accessed 
by the DSP CPU. The ICR is a read/write register that allows the use of bit 
manipulation instructions on control register bits. The control bits are described in 
the following paragraphs.

The Receive Request Enable (RREQ) bit is used to control the HOREQ pin for host 
receive data transfers. In Interrupt mode (DMA off), RREQ is used to enable 
interrupt requests via the external HI Request (HOREQ) pin when the Receive Data 
Register Full (RXDF) status bit in the ISR is set. When RREQ is cleared, RXDF 
interrupts are disabled. When RREQ is set, the external HOREQ pin will be asserted 
if RXDF is set.

In DMA modes, RREQ must be set or cleared by software to select the direction of 
DMA transfers. Setting RREQ sets the direction of DMA transfer to be DSP-to-host 
and enables the HOREQ pin to request data transfer. 

Hardware reset, software reset, individual reset, and Stop clear RREQ.

The Transmit Request enable (TREQ)

bit is used to control the HOREQ pin for host 

transmit data transfers. In Interrupt mode (DMA off), TREQ is used to enable 
interrupt requests via the external HOREQ pin when the Transmit Data register 
Empty (TXDE) status bit in the ISR is set. When TREQ is cleared, TXDE interrupts are 
disabled. When TREQ is set, the external HOREQ pin will be asserted if TXDE is set.

Figure 4-11  HI Register Map

AA0320k

$0

$1

$2

$3

$4

$5

$6

$7

Interrupt Control

Command Vector

Interrupt Status

Interrupt Vector

Unused

Receive/Transmit
Bytes

ICR

CVR

ISR

IVR

0 0 0 0 0 0 0 0

RXH/TXH

RXM/TXM

RXL/TXL

Host Address

HOA[2:0]

HI Data Bus

H[7:0]