Motorola DSP56012 User Manual

processor and the bits in the HSR and HCR used by the DSP to transfer data from the 
host processor to the DSP. The registers shown are the status register and control 
register as they are seen by the host processor, and the status register and control 
register as they are seen by the DSP. Only the registers used to transmit data from the 
host processor to the DSP are described. 

 can be summarized as follows:

1. When the TXDE bit in the ISR is set, it indicates that the Host is ready to 

receive a data byte from the host processor because the transmit byte registers 
(TXH, TXM, TXL) are empty.

2. The host processor can poll as shown in this step.

3. Alternatively, the host processor can use interrupts to determine the status of 

this bit. Setting the TREQ bit in the ICR causes the HOREQ pin to interrupt the 
host processor when TXDE is set.

4. Once the TXDE bit is set, the host can write data to the Host. It does this by 

writing three bytes to TXH, TXM, and TXL, or two bytes to TXM and TXL, or 
one byte to TXL.

5. Writing data to TXL clears TXDE in the ISR.

6. From the DSP’s viewpoint, when the HRDF bit in the HSR is set, it indicates 

that data is waiting in the Host for the DSP.

7. When the DSP reads the HORX, the HRDF bit is automatically cleared and 

TXDE in the ISR is set.

8. When TXDE = 0 and HRDF = 0, data is automatically transferred from TBR to 

HORX which sets HRDF.

9. The DSP can poll HRDF to see when data has arrived, or it can use interrupts.

10. If HRIE (in the HCR) and HRDF are set, interrupt processing is started using 

interrupt vector P:$0030.