Motorola DSP56012 User Manual
Parallel Host Interface
Host Interface (HI)
MOTOROLA
DSP56012 User’s Manual
4-59
The code shown in
data, the HTIE bit in the HCR is set instead of the HRIE bit.
The transmit routine used by the code in
on page 4-61. The interrupt vector contains a JSR, which makes it a long interrupt.
The code sends a fixed test pattern ($123456) and then resets the HI for the next
interrupt.
The code sends a fixed test pattern ($123456) and then resets the HI for the next
interrupt.
4.4.8.3
DMA Data Transfer
The DMA mode allows the transfer of 8-, 16- or 24-bit data through the DSP HI under
the control of an external DMA controller. The HI provides the pipeline data registers
and the synchronization logic between the two asynchronous processor systems. The
DSP host interrupts provide cycle-stealing data transfers with the DSP internal or
external memory. This technique allows the DSP memory address to be generated
using any of the DSP addressing modes and modifiers. Queues and circular sample
buffers are easily created for DMA transfer regions. The host interrupts can be
programmed as high priority fast or long interrupt service routines. The external
DMA controller provides the transfers between the DSP HI registers and the external
DMA memory. The external DMA controller must provide the address to the
external DMA memory; however, the address of the selected HI register is provided
by a DMA address counter in the HI.
the control of an external DMA controller. The HI provides the pipeline data registers
and the synchronization logic between the two asynchronous processor systems. The
DSP host interrupts provide cycle-stealing data transfers with the DSP internal or
external memory. This technique allows the DSP memory address to be generated
using any of the DSP addressing modes and modifiers. Queues and circular sample
buffers are easily created for DMA transfer regions. The host interrupts can be
programmed as high priority fast or long interrupt service routines. The external
DMA controller provides the transfers between the DSP HI registers and the external
DMA memory. The external DMA controller must provide the address to the
external DMA memory; however, the address of the selected HI register is provided
by a DMA address counter in the HI.
DMA transfers can only be in one direction at a time; however, the host processor can
access any of the registers not in use during the DMA transfer by deasserting HACK
and using HEN and HOA0–HOA2 to transfer data. The host can therefore transfer
data in the other direction during the DMA operation using polling techniques.
access any of the registers not in use during the DMA transfer by deasserting HACK
and using HEN and HOA0–HOA2 to transfer data. The host can therefore transfer
data in the other direction during the DMA operation using polling techniques.
Figure 4-34 Main Program: Transmit 24-bit Data to Host
**********************************************
; MAIN PROGRAM... transmit 24-bit data to host
;****************************************
ORG
P:$80
MOVEP
#1,X:PBC
;Turn on HI Port
MOVEP
#$0C00,X:IPR
;Turn on host interrupt
MOVEP
#0,X:HCR
;Turn off XMT and RCV interrupts
MOVE
#0,SR
;Unmask interrupts
JCLR
#3,X:HSR,*
;Wait for HF0 (from host) set
AND
X0,A
JEQ
LOOP
MOVEP
#$2,X:HCR
;Enable host transmit interrupt
JMP
*
;Now wait for interrupt