Motorola DSP56012 User Manual
5-24
DSP56012 User’s Manual
MOTOROLA
Serial Host Interface
SHI Programming Considerations
occurred, the contents of HTX are not transferred to IOSR, so the data that is shifted
out when receiving is the same as the data present in the IOSR at the time. The HRX
FIFO contains valid receive data, which may be read by the DSP, if the HRNE status
bit is set.
out when receiving is the same as the data present in the IOSR at the time. The HRX
FIFO contains valid receive data, which may be read by the DSP, if the HRNE status
bit is set.
The HREQ output pin, if enabled for receive (HRQE1–HRQE0 = 01), is asserted when
the IOSR is ready for receive and the HRX FIFO is not full; this operation guarantees
that the next received data word will be stored in the FIFO. The HREQ output pin, if
enabled for transmit (HRQE1–HRQE0 = 10), is asserted when the IOSR is loaded
from HTX with a new data word to transfer. If HREQ is enabled for both transmit
and receive (HRQE1–HRQE0 = 11), it is asserted when the receive and transmit
conditions are true simultaneously. HREQ is deasserted at the first clock pulse of the
next data word transfer. The HREQ line may be used to interrupt the external master
device. Connecting the HREQ line between two SHI-equipped DSPs, one operating
as an SPI master device and the other as an SPI slave device, enables full hardware
handshaking if operating with CPHA = 1.
the IOSR is ready for receive and the HRX FIFO is not full; this operation guarantees
that the next received data word will be stored in the FIFO. The HREQ output pin, if
enabled for transmit (HRQE1–HRQE0 = 10), is asserted when the IOSR is loaded
from HTX with a new data word to transfer. If HREQ is enabled for both transmit
and receive (HRQE1–HRQE0 = 11), it is asserted when the receive and transmit
conditions are true simultaneously. HREQ is deasserted at the first clock pulse of the
next data word transfer. The HREQ line may be used to interrupt the external master
device. Connecting the HREQ line between two SHI-equipped DSPs, one operating
as an SPI master device and the other as an SPI slave device, enables full hardware
handshaking if operating with CPHA = 1.
The SS line should be kept asserted during a data word transfer. If the SS line is
deasserted before the end of the data word transfer, the transfer is aborted and the
received data word is lost.
deasserted before the end of the data word transfer, the transfer is aborted and the
received data word is lost.
5.7.2
SPI Master Mode
The SPI Master mode is initiated by enabling the SHI (HEN = 1), selecting the SPI
mode (HI
mode (HI
2
C = 0), and selecting the Master mode of operation (HMST = 1). Before
enabling the SHI as an SPI master device, the programmer should program the
proper clock rate, phase, and polarity in HCKR. When configured in the SPI Master
mode, the SHI external pins operate as follows:
proper clock rate, phase, and polarity in HCKR. When configured in the SPI Master
mode, the SHI external pins operate as follows:
• SCK/SCL is the SCK serial clock output.
• MISO/SDA is the MISO serial data input.
• MOSI/HA0 is the MOSI serial data output.
• SS/HA2 is the SS input. It should be kept deasserted (high) for proper
operation.
• HREQ is the Host Request input.
The external slave device can be selected either by using external logic or by
activating a GPIO pin connected to its SS pin. However, the SS input pin of the SPI
master device should be held deasserted (high) for proper operation. If the SPI
master device SS pin is asserted, the Host Bus Error status bit (HBER) is set. If the
activating a GPIO pin connected to its SS pin. However, the SS input pin of the SPI
master device should be held deasserted (high) for proper operation. If the SPI
master device SS pin is asserted, the Host Bus Error status bit (HBER) is set. If the