Motorola DSP56012 User Manual
6-22
DSP56012 User’s Manual
MOTOROLA
Serial Audio Interface
Serial Audio Interface Programming Model
To clear TLDE or TRDE during left or right channel interrupt service, the transmit
data registers of the enabled transmitters must be written. Clearing TLDE or TRDE
will clear the respective interrupt request. If the “Transmit interrupt with exception”
indication is signaled (TLDE = TRDE = 1), then TLDE and TRDE are both cleared by
reading the TCS register, followed by writing to the transmit data register of the
enabled transmitters.
data registers of the enabled transmitters must be written. Clearing TLDE or TRDE
will clear the respective interrupt request. If the “Transmit interrupt with exception”
indication is signaled (TLDE = TRDE = 1), then TLDE and TRDE are both cleared by
reading the TCS register, followed by writing to the transmit data register of the
enabled transmitters.
Note:
Transmitters 0, 1, and 2 share the same controller. This means that the enabled
transmitters will be operating in parallel and any interrupt that is signaled will
indicate a condition on all enabled transmit data registers. The TXIE bit is
cleared during hardware reset and software reset.
transmitters will be operating in parallel and any interrupt that is signaled will
indicate a condition on all enabled transmit data registers. The TXIE bit is
cleared during hardware reset and software reset.
6.3.4.12
TCS Transmitter Interrupt Location (TXIL)—Bit 12
The read/write Transmitter Interrupt Location (TXIL) control bit selects the location
of the transmitter interrupt vectors. When TXIL = 0, the Left Channel Transmitter, the
Right Channel Transmitter, and the Transmitter Exception interrupt vectors are
located in program addresses $10, $12, and $14, respectively. When TXIL = 1, the Left
Channel Transmitter, the Right Channel Transmitter, and the Transmitter Exception
interrupt vectors are located in program addresses $40, $42, and $44, respectively.
The TXIL bit is cleared during hardware reset and software reset. Refer to Table 6-1
on page 6-9.
of the transmitter interrupt vectors. When TXIL = 0, the Left Channel Transmitter, the
Right Channel Transmitter, and the Transmitter Exception interrupt vectors are
located in program addresses $10, $12, and $14, respectively. When TXIL = 1, the Left
Channel Transmitter, the Right Channel Transmitter, and the Transmitter Exception
interrupt vectors are located in program addresses $40, $42, and $44, respectively.
The TXIL bit is cleared during hardware reset and software reset. Refer to Table 6-1
on page 6-9.
6.3.4.13
TCS Reserved Bit—Bit 13
Bit 13 in TCS is reserved and unused. It is read as 0s and should be written with 0 for
future compatibility.
future compatibility.
6.3.4.14
TCS Transmitter Left Data Empty (TLDE)—Bit 14
Transmitter Left Data Empty (TLDE) is a read-only status bit that, in conjunction
with TRDE, indicates the status of the enabled transmit data registers. TLDE is set
when the right data words (as indicated by the TLRS bit in TCS) are simultaneously
transferred from the transmit data registers to the transmit shift registers in the
enabled transmitters. This means that the transmit data registers are now free to be
loaded with the left data words. Since audio data samples are composed of left and
right data words that are transmitted alternately, normal operation of the
transmitters is achieved when only one of the status bits (TLDE or TRDE) is set at a
time. A transmit underrun condition is indicated when both TLDE and TRDE are set.
TLDE is cleared when the DSP writes to the transmit data registers of the enabled
transmitters, provided that
with TRDE, indicates the status of the enabled transmit data registers. TLDE is set
when the right data words (as indicated by the TLRS bit in TCS) are simultaneously
transferred from the transmit data registers to the transmit shift registers in the
enabled transmitters. This means that the transmit data registers are now free to be
loaded with the left data words. Since audio data samples are composed of left and
right data words that are transmitted alternately, normal operation of the
transmitters is achieved when only one of the status bits (TLDE or TRDE) is set at a
time. A transmit underrun condition is indicated when both TLDE and TRDE are set.
TLDE is cleared when the DSP writes to the transmit data registers of the enabled
transmitters, provided that
When a transmit underrun
condition occurs,
the previous data (which is still present in the
data registers) will be re-transmitted. In this case, TLDE is cleared by first reading the
TCS register, followed by writing the transmit data registers of the enabled
transmitters. If TXIE is set, an interrupt request will be issued when TLDE is set. The
vector of the interrupt request will depend on the state of the transmit underrun
TCS register, followed by writing the transmit data registers of the enabled
transmitters. If TXIE is set, an interrupt request will be issued when TLDE is set. The
vector of the interrupt request will depend on the state of the transmit underrun
(TLDE
TRDE
⊕
1).
=
(TLDE
TRDE
•
1),
=