Motorola DSP56012 User Manual

The XAUR bit is cleared by reading the XSTR register with XAUR set, 
followed by writing data to XADRA and XADRB. It is also cleared by software 
reset and hardware reset, and by the Stop state.

The XBLK flag indicates that the frame being transmitted is the last frame in a block. 
This bit is set at the beginning of the transmission of the last frame (the 191st frame). 
This bit does not cause any interrupt. However, it causes a change in the interrupt 
vector sent to DSP core in the event of an interrupt, so that a different interrupt 
routine can be called (providing the next non-audio data structures for the next block 
as well as storing audio data for the next frame). Writing to XADRA and XADRB 
clears this bit. 

Software reset, hardware reset, and the Stop state clear XBLK.

The relative timing of transmit frames and XADE and XBLK flags is shown in 

The XTIP status flag indicates that the DAX is enabled and transmitting data. When 
XTIP is set, it indicates that the DAX is active. When XTIP is cleared, it indicates that 
the DAX is inactive. This bit provides programmers with the means to determine 
whether the DAX is active or inactive. Since the DAX can be active and transmitting 
data even after the XEN bit in the XCTR has been cleared (with XSTP = 1), it can be 
necessary to know when the DAX actually becomes inactive. This bit is set a moment 
after the DAX is enabled (XEN = 1). It is cleared either immediately (by clearing the 
XEN bit, when XSTP = 0), or it is cleared at the next frame boundary (if XSTP = 1). 

Software reset, hardware reset, and the Stop state clear XTIP immediately.

Figure 8-3  DAX Relative Timing

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XADE

XBLK

Frame

XADE

XBLK

Frame

XADE

XBLK

Frame

#168 #169

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