Motorola DSP56012 User Manual
Signal Descriptions
OnCE Port
MOTOROLA
DSP56012 User’s Manual
2-19
2.11
OnCE PORT
Table 2-12
On-Chip Emulation Port (OnCE) Signals
Signal
Name
Signal
Type
State
during
Reset
Signal Description
DSI/OS0
Input/O
utput
Low
Output
Debug Serial Input/Chip Status 0—
Serial data or commands
are provided to the OnCE controller through the DSI/OS0
signal when it is an input. The data received on the DSI signal
will be recognized only when the DSP has entered the Debug
mode of operation. Data is latched on the falling edge of the
DSCK serial clock. Data is always shifted into the OnCE serial
port Most Significant Bit (MSB) first. When the DSI/OS0 signal
is an output, it works in conjunction with the OS1 signal to
provide chip status information. The DSI/OS0 signal is an
output when the processor is not in Debug mode. When
switching from output to input, the signal is tri-stated.
signal when it is an input. The data received on the DSI signal
will be recognized only when the DSP has entered the Debug
mode of operation. Data is latched on the falling edge of the
DSCK serial clock. Data is always shifted into the OnCE serial
port Most Significant Bit (MSB) first. When the DSI/OS0 signal
is an output, it works in conjunction with the OS1 signal to
provide chip status information. The DSI/OS0 signal is an
output when the processor is not in Debug mode. When
switching from output to input, the signal is tri-stated.
Note:
If the OnCE interface is in use, an external pull-down resistor
should be attached to this pin. If the OnCE interface is not in
use, the resistor is not required.
should be attached to this pin. If the OnCE interface is not in
use, the resistor is not required.
DSCK/
OS1
OS1
Input/O
utput
Low
Output
Debug Serial Clock/Chip Status 1—
The DSCK/OS1 signal
supplies the serial clock to the OnCE when it is an input. The
serial clock provides pulses required to shift data into and out
of the OnCE serial port. (Data is clocked into the OnCE on the
falling edge and is clocked out of the OnCE serial port on the
rising edge.) The debug serial clock frequency must be no
greater than
serial clock provides pulses required to shift data into and out
of the OnCE serial port. (Data is clocked into the OnCE on the
falling edge and is clocked out of the OnCE serial port on the
rising edge.) The debug serial clock frequency must be no
greater than
1
/
8
of the processor clock frequency. When
switching from input to output, the signal is tri-stated.
When it is an output, this signal works with the OS0 signal to
provide information about the chip status. The DSCK/OS1
signal is an output when the chip is not in Debug mode.
provide information about the chip status. The DSCK/OS1
signal is an output when the chip is not in Debug mode.
Note:
If the OnCE interface is in use, an external pull-down resistor
should be attached to this pin. If the OnCE interface is not in
use, the resistor is not required.
should be attached to this pin. If the OnCE interface is not in
use, the resistor is not required.