Motorola DSP56012 User Manual
Memory, Operating Modes, and Interrupts
DSP56012 Data and Program Memory Maps
MOTOROLA
DSP56012 User’s Manual
3-9
• No accesses (including instruction fetches) to/from P:$0200–$0AFF are
allowed during the switch cycle.
Note:
The switch actually occurs three instruction cycles after the instruction
that modifies the PEA/PEB bits.
that modifies the PEA/PEB bits.
Any sequence that complies with the switch conditions is valid. For example, if the
program flow executes in the address range that is not affected by the switch (other
than P:$0200–$0AFF), the switch conditions can be met very easily. In this case a
switch can be accomplished by just changing PEA/PEB bits in OMR in the regular
program flow, assuming no accesses to X:$0A00–$0FFF or Y:$0E00–$10FF occur up to
three instructions after the instruction that changes the OMR bits.
program flow executes in the address range that is not affected by the switch (other
than P:$0200–$0AFF), the switch conditions can be met very easily. In this case a
switch can be accomplished by just changing PEA/PEB bits in OMR in the regular
program flow, assuming no accesses to X:$0A00–$0FFF or Y:$0E00–$10FF occur up to
three instructions after the instruction that changes the OMR bits.
A more intricate case is one in which switch memory operation takes place while the
program flow is being executed (or should proceed) in the affected program address
range (P:$0200–$0AFF). In this case, a particular switch sequence should be
performed. Interrupts must be disabled before executing the switch sequence, since
an interrupt could cause the DSP to fetch instructions out of sequence. The interrupts
must be disabled at least four instruction cycles before switching, due to pipeline
latency of the interrupt processing.
program flow is being executed (or should proceed) in the affected program address
range (P:$0200–$0AFF). In this case, a particular switch sequence should be
performed. Interrupts must be disabled before executing the switch sequence, since
an interrupt could cause the DSP to fetch instructions out of sequence. The interrupts
must be disabled at least four instruction cycles before switching, due to pipeline
latency of the interrupt processing.
Special attention should be given when running a memory switch routine using the
OnCE port. Running the switch routine in Trace mode, for example, can cause the
switch to complete after the PEA/PEB bit changes while the DSP is in Debug mode.
As a result, subsequent instructions might be fetched according to the new memory
configuration (after the switch), and thus might execute improperly. A general
purpose routine in which the switch conditions are always met, independent of
where the program flow originates (before the switch) or where it proceeds (after the
switch), is shown below:
OnCE port. Running the switch routine in Trace mode, for example, can cause the
switch to complete after the PEA/PEB bit changes while the DSP is in Debug mode.
As a result, subsequent instructions might be fetched according to the new memory
configuration (after the switch), and thus might execute improperly. A general
purpose routine in which the switch conditions are always met, independent of
where the program flow originates (before the switch) or where it proceeds (after the
switch), is shown below:
;Switch to Program RAM enabled:
ORI
#03,MR
; Disable interrupts
INST1
; Four instruction cycles guarantee no interrupts
INST2
; after interrupts were disabled.
INST3
; INST# denotes a one-word instruction, however,
INST4
; two one-word instructions can be replaced by
; one two-word instruction.
ORI
#$C,OMR
; Set PEA/PEB bits in OMR
ANDI
#$FC,MR
; Allow a delay for remapping,
; meanwhile re-enable interrupts
JMP
>Next_Address
; 2-word (long) jump instruction (uninterruptable)
;Switch to Program RAM disabled:
ORI
#03,MR
; Disable interrupts
INST1
; Four instruction cycles guarantee no interrupts
INST2
; after interrupts were disabled.
INST3
; INST# denotes any one-word instruction, however,
INST4
; two one-word instructions can be replaced by
; one two-word instruction.