Motorola DSP56012 User Manual
3-14
DSP56012 User’s Manual
MOTOROLA
Memory, Operating Modes, and Interrupts
Operating Modes
ends up in the first location of the Program ROM (program address
$0A00).
$0A00).
Note:
It is not possible to reach operating Mode 4 during hardware reset. Any
attempt to start up in Mode 4 defaults to Mode 1.
attempt to start up in Mode 4 defaults to Mode 1.
Mode 5
In this mode, the bootstrap ROM is enabled and the bootstrap
program is executed after hardware reset. The internal Program RAM
is loaded with 256 words from the Serial Host Interface (SHI). The SHI
operates in the SPI Slave mode, with 24-bit word width.
program is executed after hardware reset. The internal Program RAM
is loaded with 256 words from the Serial Host Interface (SHI). The SHI
operates in the SPI Slave mode, with 24-bit word width.
Mode 6
Reserved.
Note:
It is not possible to reach operating Mode 6 during hardware reset. Any
attempt to start up in Mode 6 defaults to Mode 1.
attempt to start up in Mode 6 defaults to Mode 1.
Mode 7
In this mode, the bootstrap ROM is enabled and the bootstrap
program is executed after hardware reset. The internal Program RAM
is loaded with 256 oords from the Serial Host Interface (SHI). The SHI
operates in the I
program is executed after hardware reset. The internal Program RAM
is loaded with 256 oords from the Serial Host Interface (SHI). The SHI
operates in the I
2
C Slave mode, with 24-bit word width.
Note:
The OnCE port operation is enabled at hardware reset. This means the
device can enter the Debug mode at any time after hardware reset.
device can enter the Debug mode at any time after hardware reset.