Motorola DSP56012 User Manual

For pins configured as GPIO by the PBC Register, the Port B Data Direction Register 
(PBDDR) determines whether the pins are inputs (bit = 0) or outputs (bit = 1). 

The default setting after reset is input.

The Port B Data (PBD) register provides access to the fifteen Port B pins as follows:

• If a pin is configured as a GPIO input and the processor reads the PBD 

register, the processor sees the logic level on the pin. If the processor writes to 
the PBD register, the data is latched there, but does not appear on the pin 
because the buffer is in the high-impedance state.

• If a pin is configured as a GPIO output and the processor reads the PBD 

register, the processor sees the contents of the PBD register rather than the 
logic level on the pin, which allows the PBD register to be used as a general 
purpose register. If the processor writes to the PBD register, the data is latched 
there and appears on the pin during the following instruction cycle.

If a pin is configured as a host pin, the Port B GPIO registers can help in 
debugging HI operations. If the PBDDR bit for a given pin configured as an 
input (i.e., 0), the PBD register shows the logic level on the pin, regardless of 
whether the HI function is using the pin as an input or an output. If the 
PBDDR is set (configured as an output) for a pin that is configured as a host 
pin, when the processor reads the PBD register, it sees the contents of the PBD 
register rather than the logic level on the pin—another case that allows the 
PBD register to act as a general purpose register.

The external host processor should be carefully synchronized to the DSP56012 
to assure that the DSP and the external host properly read status bits 
transmitted between them. There is more discussion of such port usage issues 
in 

 

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