Motorola DSP56012 User Manual
Parallel Host Interface
Host Interface (HI)
MOTOROLA
DSP56012 User’s Manual
4-15
portion is 0-filled. Any reserved bits are read as 0s and should be written with 0s for
compatibility with future revisions. Bit manipulation instructions are useful for
accessing the individual bits in the HCR. The control bits are described in the
following paragraphs.
compatibility with future revisions. Bit manipulation instructions are useful for
accessing the individual bits in the HCR. The control bits are described in the
following paragraphs.
Note:
The contents of the HCR are cleared by hardware reset or software reset.
4.4.4.1.1
HCR HI Receive Interrupt Enable (HRIE)—Bit 0
The HI Receive Interrupt Enable (HRIE) bit is used to enable a DSP interrupt when
the HI Receive Data Full (HRDF) status bit in the HI Status Register (HSR) is set.
When HRIE is cleared, HRDF interrupts are disabled. When HRIE is set, a host
receive data interrupt request will occur if HRDF is also set.
the HI Receive Data Full (HRDF) status bit in the HI Status Register (HSR) is set.
When HRIE is cleared, HRDF interrupts are disabled. When HRIE is set, a host
receive data interrupt request will occur if HRDF is also set.
Note:
Hardware reset and software reset clear HRIE.
4.4.4.1.2
HCR HI Transmit Interrupt Enable (HTIE)—Bit 1
The HI Transmit Interrupt Enable (HTIE) bit is used to enable a DSP interrupt when
the HI Transmit Data Empty (HTDE) status bit in the HSR is set. When HTIE is
cleared, HTDE interrupts are disabled. When HTIE is set, a host transmit data
interrupt request will occur if HTDE is also set.
the HI Transmit Data Empty (HTDE) status bit in the HSR is set. When HTIE is
cleared, HTDE interrupts are disabled. When HTIE is set, a host transmit data
interrupt request will occur if HTDE is also set.
Note:
Hardware reset and software reset clear the HTIE.
4.4.4.1.3
HCR HI Command Interrupt Enable (HCIE)—Bit 2
The HI Command Interrupt Enable (HCIE) bit is used to enable a vectored DSP
interrupt when the HI Command Pending (HCP) status bit in the HSR is set. When
HCIE is cleared, HCP interrupts are disabled. When HCIE is set, a host command
interrupt request will occur if HCP is also set. The starting address of this interrupt is
determined by the HI Vector (HV).
interrupt when the HI Command Pending (HCP) status bit in the HSR is set. When
HCIE is cleared, HCP interrupts are disabled. When HCIE is set, a host command
interrupt request will occur if HCP is also set. The starting address of this interrupt is
determined by the HI Vector (HV).
Note:
Hardware reset and software reset clear the HCIE.
4.4.4.1.4
HCR HI Flag 2 (HF2)—Bit 3
The HI Flag 2 (HF2) bit is used as a general purpose flag for DSP-to-host
communication. HF2 can be set or cleared by the DSP. HF2 is visible to the host
processor in the Interrupt Status Register (ISR) (see
communication. HF2 can be set or cleared by the DSP. HF2 is visible to the host
processor in the Interrupt Status Register (ISR) (see
Note:
Hardware reset and software reset clear HF2.
4.4.4.1.5
HCR HI Flag 3 (HF3)—Bit 4
The HI Flag 3 (HF3) bit is used as a general purpose flag for DSP-to-host
communication. HF3 can be set or cleared by the DSP. HF3 is visible to the host
processor in the ISR (see
communication. HF3 can be set or cleared by the DSP. HF3 is visible to the host
processor in the ISR (see