Intel Xeon E5502 80602E5502 User Manual

Product codes
80602E5502
Page of 130
Intel® Xeon® Processor 5500 Series Datasheet, Volume 2
105
Register Description
2.15.25 MC_CHANNEL_0_MAINTENANCE_OPS
MC_CHANNEL_1_MAINTENANCE_OPS
MC_CHANNEL_2_MAINTENANCE_OPS
This register enables various maintenance operations such as ZQ, RCOMP, etc.
2.15.26 MC_CHANNEL_0_TX_BG_SETTINGS
MC_CHANNEL_1_TX_BG_SETTINGS
MC_CHANNEL_2_TX_BG_SETTINGS
These are the parameters used to set the Start Scheduler for TX clock crossing. This is 
used to send commands to the DIMMs.
The NATIVE RATIO is UCLK multiplier of BCLK = U
ALIEN RATION is DCLK multiplier of BCLK = D
PIPE DEPTH = 8 UCLK (design dependent variable)
MIN SEP DELAY = 670ps (design dependent variable, Internally this is logic delay of 
FIFO + clock skew between U and D)
TOTAL EFFECTIVE DELAY = PIPE DEPTH * UCLK PERIOD in ps + MIN SEP DELAY
DELAY FRACTION = (TOTAL EFFECTIVE DELAY * D) / (UCLK PERIOD in ps * G.C.D(U,D)
Determine OFFSET MULTIPLE using the equation 
FLOOR ((OFFSET MULTIPLE +1) / G.C.D (U,D)) > DELAY FRACTION
OFFSET VALUE = MOD (OFFSET MULTIPLE, U) <= Final answer for OFFSET MULTIPLE
Device:
4, 5, 6
Function: 0
Offset:
BCh
Access as a Dword
Bit
Type
Reset
Value
Description
12:0
RW
0
MAINT_CNTR. Value to be loaded in the maintenance counter. This counter 
sequences the rate to ZQ, RCOMP in increments of maintenance counter 
intervals.
Device:
4, 5, 6
Function: 0
Offset:
C0h
Access as a Dword
Bit
Type
Reset
Value
Description
23:16
RW
2
OFFSET. TX offset setting.
15:8
RW
1
ALIENRATIO. Dclk ratio to BCLK. TX Alien Ratio setting.
7:0
RW
4
NATIVERATIO. Uclk ratio to BCLK. TX Native Ratio setting.