Intel Xeon E5502 80602E5502 User Manual

Product codes
80602E5502
Page of 130
Register Description
106
Intel® Xeon® Processor 5500 Series Datasheet, Volume 2
2.15.27 MC_CHANNEL_0_RX_BGF_SETTINGS
MC_CHANNEL_1_RX_BGF_SETTINGS
MC_CHANNEL_2_RX_BGF_SETTINGS
These are the parameters used to set the Rx clock crossing BGF.
2.15.28 MC_CHANNEL_0_EW_BGF_SETTINGS
MC_CHANNEL_1_EW_BGF_SETTINGS
MC_CHANNEL_2_EW_BGF_SETTINGS
These are the parameters used to set the early warning RX clock crossing BGF.
2.15.29 MC_CHANNEL_0_EW_BGF_OFFSET_SETTINGS
MC_CHANNEL_1_EW_BGF_OFFSET_SETTINGS
MC_CHANNEL_2_EW_BGF_OFFSET_SETTINGS
These are the parameters to set the early warning RX clock crossing BGF.
Device:
4, 5, 6
Function: 0
Offset:
C8h
Access as a Dword
Bit
Type
Reset
Value
Description
26:24
RW
2
PTRSEP. RX FIFO pointer separation settings. THIS FIELD IS NOT USED BY 
HARDWARE. RX Pointer separation can be modified via the round trip setting 
(larger value causes a larger pointer separation).
23:16
RW
0
OFFSET. RX offset setting.
15:8
RW
1
ALIENRATIO. Qclk to BCLK ratio. RX Alien Ratio setting.
7:0
RW
2
NATIVERATIO. Uclk to BCLK ratio. RX Native Ratio setting.
Device:
4, 5, 6
Function: 0
Offset:
CCh
Access as a Dword
Bit
Type
Reset
Value
Description
15:8
RW
1
ALIENRATIO. Dclk to Bclk ratio. Early warning Alien Ratio setting.
Device:
4, 5, 6
Function: 0
Offset:
D0h
Access as a Dword
Bit
Type
Reset
Value
Description
15:8
RW
2
EVENOFFSET. Early warning even offset setting.
7:0
RW
0
ODDOFFSET. Early warning odd offset setting.