Intel Xeon E5502 80602E5502 User Manual
Product codes
80602E5502
Intel® Xeon® Processor 5500 Series Datasheet, Volume 2
119
Register Description
2.18.2
MC_THERMAL_STATUS0
MC_THERMAL_STATUS1
MC_THERMAL_STATUS2
Status registers for the thermal throttling logic for each channel.
2.18.3
MC_THERMAL_DEFEATURE0
MC_THERMAL_DEFEATURE1
MC_THERMAL_DEFEATURE2
Thermal Throttle defeature register for each channel.
2.18.4
MC_THERMAL_PARAMS_A0
MC_THERMAL_PARAMS_A1
MC_THERMAL_PARAMS_A2
Parameters used by Open Loop Throughput Throttling (OLTT) and Closed Loop Thermal
Throttling (CLTT).
Throttling (CLTT).
Device:
4, 5, 6
Function: 3
Offset:
4Ch
Access as a Dword
Bit
Type
Reset
Value
Description
29:4
RO
0
CYCLES_THROTTLED. The number of throttle cycles, in increments of 256
Dclks, triggered in any rank in the last SAFE_INTERVAL number of ZQs.
3:0
RO
0
RANK_TEMP. The bit specifies whether the rank is above throttling threshold.
Device:
4, 5, 6
Function: 3
Offset:
50h
Access as a Dword
Bit
Type
Reset
Value
Description
0
RW1S
0
THERM_REG_LOCK. When set, no further modification of all thermal throttle
registers are allowed. This bit must be set to the same value for all channels.
Device:
4, 5, 6
Function: 3
Offset:
60h
Access as a Dword
Bit
Type
Reset
Value
Description
31:24
RW
0
CKE_ASSERT_ENERGY. Energy of having CKE asserted when no command is
issued.
23:16
RW
0
CKE_DEASSERT_ENERGY. Energy of having CKE de-asserted when no
command is issued.
15:8
RW
0
WRCMD_ENERGY. Energy of a write including data transfer.
7:0
RW
0
RDCMD_ENERGY. Energy of a read including data transfer.