Intel Xeon E5502 80602E5502 User Manual

Product codes
80602E5502
Page of 130
Register Description
60
Intel® Xeon® Processor 5500 Series Datasheet, Volume 2
2.7.5
SAD_PCIEXBAR
Global register for PCIEXBAR address space.
2.7.6
SAD_DRAM_RULE_0
SAD_DRAM_RULE_1
SAD_DRAM_RULE_2
SAD_DRAM_RULE_3
SAD_DRAM_RULE_4
SAD_DRAM_RULE_5
SAD_DRAM_RULE_6
SAD_DRAM_RULE_7
SAD DRAM rules. Address Map for package determination.
Device:
0
Function: 1
Offset:
50h
Access as a Qword
Bit
Type
Reset
Value
Description
39:20
RW
0
ADDRESS. Base address of PCIEXBAR. Must be naturally aligned to size; low 
order bits are ignored.
3:1
RW
0
SIZE. Size of the PCIEXBAR address space. (MAX bus number).
000: 256MB.
001: Reserved.
010: Reserved.
011: Reserved.
100: Reserved.
101: Reserved.
110: 64MB.
111: 128MB.
0
RW
0
ENABLE. Enable for PCIEXBAR address space. Editing size should not be done 
without also enabling range.
Device:
0
Function: 1
Offset:
80h, 84h, 88h, 8Ch, 90h, 94h, 98h, 9Ch
Access as a Dword
Bit
Type
Reset
Value
Description
19:6
RW
-
LIMIT. DRAM rule top limit address. Must be strictly greater than previous rule, 
even if this rule is disabled, unless this rule and all following rules are disabled. 
Lower limit is the previous rule (or 0 if it is first rule). This field is compared 
against MA[39:26] in the memory address map.
2:1
RW
-
MODE. DRAM rule interleave mode. If a DRAM_RULE hits a 3 bit number is 
used to index into the corresponding interleave_list to determine which 
package the DRAM belongs to. This mode selects how that number is 
computed. 
00: Address bits {8,7,6}. 
01: Address bits {8,7,6} XORed with {18,17,16}. 
10: Address bit {6}, MOD3(Address[39..6]). (Note 6 is the high order bit) 
11: Reserved.
0
RW
0
ENABLE. Enable for DRAM rule. If Enabled Range between this rule and 
previous rule is Directed to HOME channel (unless overridden by other 
dedicated address range registers). If disabled, all accesses in this range are 
directed in MMIO to the IOH.