Intel Xeon E5502 80602E5502 User Manual

Product codes
80602E5502
Page of 130
Register Description
62
Intel® Xeon® Processor 5500 Series Datasheet, Volume 2
2.8.2
QPI_QPILCL_L0
QPI_QPILCL_L1
Intel QPI Link Control.
23:22
RO
-
VN0_CRDTS_NDATA. VN0 Credits per Non-Data MC 
00 - 0 credits 
01 - 1 
10 - 2 to 8 
11 - RSVD
21:16
RO
-
VNA_CRDTS. VNA Credits / 8, after rounding down.
11
RO
-
CRC_SUPPORT. CRC Mode Support.
0 - 8b CRC.
1 - RSVD
9:8
RO
-
FLIT_INTERLEAVE. Flit Interleave.
00 - Idle/Null flit only.
01 - Command Insert Interleave.
10 - RSVD.
11 - RSVD.
7:0
RO
-
QPI_VER. Intel QPI Version Number
0 - Rev 1.0
!0 - RSVD.
Device:
2
Function: 0, 4
Offset:
40h
Access as a Dword
Bit
Type
Reset
Value
Description
Device:
2
Function: 0, 4
Offset:
48h
Access as a Dword
Bit
Type
Reset
Value
Description
21
RW
0
L1_MASTER. Indicates that this end of the link is the L1 master. This link
transmitter bit is an L1 power state master and can initiate an L1 power state
transition. If this bit is not set, then the link transmitter is an L1 power state
slave and should respond to L1 transitions with an ACK or NACK.
If the link power state of L1 is enabled, then there is one master and one slave
per link. The master may only issue single L1 requests, while the slave can only
issue single L1_Ack or L1_NAck responses for the corresponding request.
20
RW
0
L1_ENABLE. Enables L1 mode at the transmitter. This bit should be ANDed
with the receive L1 capability bit received during parameter exchange to
determine if a transmitter is allowed to enter into L1. This is NOT a bit that
determines the capability of a device. 
18
RW
0
L0S_ENABLE. Enables L0s mode at the transmitter. This bit should be ANDed
with the receive L0s capability bit received during parameter exchange to
determine if a transmitter is allowed to enter into L0s. This is NOT a bit that
determines the capability of a device.