Intel Xeon E5502 80602E5502 User Manual
Product codes
80602E5502
Intel® Xeon® Processor 5500 Series Datasheet, Volume 2
67
Register Description
2.9.2
QPI_0_PH_CTR
QPI_1_PH_CTR
Intel QPI Physical Layer Control Register.
21:20
RO
-
RAS_CAPABILITY. Any of these bits set indicates Alternate Clock RAS
capability available and that corresponding control bits in QPI_*_PH_CTR are
implemented.
17:16
RO
-
DETERMINISM_SUPPORT. Determinism supported mode of operations.
Bit17: If set, Master mode of operation supported. Component Specification or
equivalent document should contain the information about PhyL0Synch.
Bit16: If set, Slave mode of operation supported.
10:8
RO
-
LINK_WIDTH_CAPABILITY. Bit8: If set, Full Width capable.
7:5
RO
0
DEBUG_CAPABILITY. Bit7: If set, an implementation is not capable of
extracting slave electrical parameter from TS.Loopback and apply during the
test.
Bit6: If set, an implementation is not capable of running in Compliance slave
mode as well as transitioning to Loopback.Pattern from Compliance state.
Bit5: If set, an implementation is not capable of doing Loopcount Stal
4
RO
0
RETRAIN_GRANULARITY. If set, implementation is capable of 16UI
granularity in retraining duration.
3:0
RO
-
PHY_VERSION. This is the Intel QPI Phy version.
0: Current Intel QPI version 0.
Rest are reserved.
0: Current Intel QPI version 0.
Rest are reserved.
Device:
2
Function: 1, 5
Offset:
68h
Access as a Dword
Bit
Type
Reset
Value
Description
Device:
2
Function: 1, 5
Offset:
6Ch
Access as a Dword
Bit
Type
Reset
Value
Description
27
RW
0
LA_LOAD_DISABLE. Disables the loading of the effective values of the Intel
QPI CSRs when set.
23
RW
0
ENABLE_PRBS. Enables LFSR pattern during bitlock/training.
1 - use pattern in bitlock/retraining.
0 - use clock pattern for bitlock/retraining.
1 - use pattern in bitlock/retraining.
0 - use clock pattern for bitlock/retraining.
22
RW
0
ENABLE_SCRAMBLE. Enables data scrambling through LFSR.
1 - data scrambled/descrambled with LFSR
0 - data not scrambled/descrambled.
1 - data scrambled/descrambled with LFSR
0 - data not scrambled/descrambled.
15:14
RW
2
DETERMINISM_MODE. Sets determinism mode of operation.
00 - Non-deterministic initialization.
01 - Slave mode initialization.
10 - Master mode of initialization - valid only if a component can generate its
PhyL0Synch.
00 - Non-deterministic initialization.
01 - Slave mode initialization.
10 - Master mode of initialization - valid only if a component can generate its
PhyL0Synch.
13
RW
1
DISABLE_AUTO_COMP. Disables automatic entry into compliance.
0 - path from detect.clkterm to compliance is allowed.
1 - path from detect.clkterm to compliance is disabled.
0 - path from detect.clkterm to compliance is allowed.
1 - path from detect.clkterm to compliance is disabled.
12
RW
0
INIT_FREEZE. When set, freezes the FSM when initialization aborts.