Intel Xeon E5502 80602E5502 User Manual

Product codes
80602E5502
Page of 130
Intel® Xeon® Processor 5500 Series Datasheet, Volume 2
69
Register Description
2.9.4
QPI_0_PH_PTV
QPI_1_PH_PTV
Intel QPI Physical Layer Initialization Primary Timeout Value Register.
2.9.5
QPI_0_PH_LDC
QPI_1_PH_LDC
Intel QPI Physical Layer Link Determinism Control Register.
Device:
2
Function: 1, 5
Offset:
94h
Access as a Dword
Bit
Type
Reset
Value
Description
19:16
RW
0
POLLING_BITLOCK. Exponential count for Polling Bitlock. Timeout value is 
2^(count in this field)*128 TSL.
11:8
RW
1
INBAND_RESET. Exponential count for Inband_Reset_Init. Time-out value is 
2^(count in this field)*128 TSL.
3:0
RW
2
DEBOUNCE. Exponential count for debounce.
Device:
2
Function: 1, 5
Offset:
9Ch
Access as a Dword
Bit
Type
Reset
Value
Description
23:16
RW
0
TARGET_LINK_LATENCY. This field specifies the target link latency value in 
UI that the remote port needs to adjust to.
11:8
RW
5
DRIFT_BUF_DEPTH. The default pointer separation for the Intel QPI Rx PI 
FIFO.
3:0
RW
2
DRIFT_ALARM_THRESHOLD. Intel QPI RX PI FIFO alarm threshold.