Intel Xeon E5502 80602E5502 User Manual
Product codes
80602E5502
Intel® Xeon® Processor 5500 Series Datasheet, Volume 2
75
Register Description
2.11.4
MC_SMI_CNTRL
System Management Interrupt control register.
11:0
RW0C
0
DIMM_ERROR_OVERFLOW_STATUS. This 12-bit field is the per dimm error
overflow status bits. The organization is as follows:
If there are three or more DIMMS on the channel:
Bit 0 : Dimm 0 Channel 0
Bit 1 : Dimm 1 Channel 0
Bit 2 : Dimm 2 Channel 0
Bit 3 : Dimm 3 Channel 0
Bit 4 : Dimm 0 Channel 1
Bit 5 : Dimm 1 Channel 1
Bit 6 : Dimm 2 Channel 1
Bit 7 : Dimm 3 Channel 1
Bit 8 : Dimm 0 Channel 2
Bit 9 : Dimm 1 Channel 2
Bit 10 : Dimm 2 Channel 2
Bit 11 : Dimm 3 Channel 2
If there are three or more DIMMS on the channel:
Bit 0 : Dimm 0 Channel 0
Bit 1 : Dimm 1 Channel 0
Bit 2 : Dimm 2 Channel 0
Bit 3 : Dimm 3 Channel 0
Bit 4 : Dimm 0 Channel 1
Bit 5 : Dimm 1 Channel 1
Bit 6 : Dimm 2 Channel 1
Bit 7 : Dimm 3 Channel 1
Bit 8 : Dimm 0 Channel 2
Bit 9 : Dimm 1 Channel 2
Bit 10 : Dimm 2 Channel 2
Bit 11 : Dimm 3 Channel 2
If there are one or two DIMMS on the channel:
Bit 0 : Dimm 0, Ranks 0 and 1, Channel 0
Bit 1 : Dimm 0, Ranks 2 and 3, Channel 0
Bit 2 : Dimm 1, Ranks 0 and 1, Channel 0
Bit 3 : Dimm 1, Ranks 2 and 3, Channel 0
Bit 4 : Dimm 0, Ranks 0 and 1, Channel 1
Bit 5 : Dimm 0, Ranks 2 and 3, Channel 1
Bit 6 : Dimm 1, Ranks 0 and 1, Channel 1
Bit 7 : Dimm 1, Ranks 2 and 3, Channel 1
Bit 8 : Dimm 0, Ranks 0 and 1, Channel 2
Bit 9 : Dimm 0, Ranks 2 and 3, Channel 2
Bit 10 : Dimm 1, Ranks 0 and 1, Channel 2
Bit 11 : Dimm 1, Ranks 2 and 3, Channel 2
Bit 0 : Dimm 0, Ranks 0 and 1, Channel 0
Bit 1 : Dimm 0, Ranks 2 and 3, Channel 0
Bit 2 : Dimm 1, Ranks 0 and 1, Channel 0
Bit 3 : Dimm 1, Ranks 2 and 3, Channel 0
Bit 4 : Dimm 0, Ranks 0 and 1, Channel 1
Bit 5 : Dimm 0, Ranks 2 and 3, Channel 1
Bit 6 : Dimm 1, Ranks 0 and 1, Channel 1
Bit 7 : Dimm 1, Ranks 2 and 3, Channel 1
Bit 8 : Dimm 0, Ranks 0 and 1, Channel 2
Bit 9 : Dimm 0, Ranks 2 and 3, Channel 2
Bit 10 : Dimm 1, Ranks 0 and 1, Channel 2
Bit 11 : Dimm 1, Ranks 2 and 3, Channel 2
Device:
3
Function: 0
Offset:
50h
Access as a Dword
Bit
Type
Reset
Value
Description
Device:
3
Function: 0
Offset:
54h
Access as a Dword
Bit
Type
Reset
Value
Description
16
RW
0
INTERRUPT_SELECT_NMI. NMI enable. Set to enable NMI signaling. Clear to
disable NMI signaling. If both NMI and SMI enable bits are set, then only SMI is
sent.
15
RW
0
INTERRUPT_SELECT_SMI. SMI enable. Set to enable SMI signaling. Clear to
disable SMI signaling. If both NMI and SMI enable bits are set, then only SMI is
sent. This bit functions the same way in Mirror and Independent Modes.
The possible SMI events enabled by this bit are:
Any one of the error counters MC_COR_ECC_CNT_X meets the value of
The possible SMI events enabled by this bit are:
Any one of the error counters MC_COR_ECC_CNT_X meets the value of
SMI_ERROR_THRESHOLD field of this register.
MC_RAS_STATUS.REDUNDANCY_LOSS bit is set to 1.
14:0
RW
0
SMI_ERROR_THRESHOLD. Defines the error threshold to compare against
the per-DIMM error counters MC_COR_ECC_CNT_X, which are also 15 bits.