Intel Xeon E5502 80602E5502 User Manual

Product codes
80602E5502
Page of 130
Register Description
76
Intel® Xeon® Processor 5500 Series Datasheet, Volume 2
2.11.5
MC_RESET_CONTROL
DIMM Reset enabling controls.
2.11.6
MC_CHANNEL_MAPPER
Channel mapping register. The sequence of operations to update this register is:
Read MC_Channel_Mapper register
Compare data read to data to be written. If different then write.
Poll MC_Channel_Mapper register until the data read matches data written. 
Device:
3
Function: 0
Offset:
5Ch
Access as a Dword
Bit
Type
Reset
Value
Description
0
WO
0
BIOS_RESET_ENABLE. When set, MC takes over control of driving RESET to 
the DIMMs. This bit is set on S3 exit and cold boot to take over RESET driving 
responsibility from the physical layer. 
Device:
3
Function: 0
Offset:
60h
Access as a Dword
Bit
Type
Reset
Value
Description
17:15
RW
0
RDLCH2. Mapping of Logical Channel 2 to physical channel for Reads.
001 - Maps to physical Channel 0
010 - Maps to physical Channel 1
100 - Maps to physical Channel 2
14:12
RW
0
WRLCH2. Mapping of Logical Channel 2 to physical channel for Writes.
001 - Maps to physical Channel 0
010 - Maps to physical Channel 1
100 - Maps to physical Channel 2
11:9
RW
0
RDLCH1. Mapping of Logical Channel 1 to physical channel for Reads.
001 - Maps to physical Channel 0
010 - Maps to physical Channel 1
100 - Maps to physical Channel 2
8:6
RW
0
WRLCH1. Mapping of Logical Channel 1 to physical channel for Writes.
001 - Maps to physical Channel 0
010 - Maps to physical Channel 1
100 - Maps to physical Channel 2
5:3
RW
0
RDLCH0. Mapping of Logical Channel 0 to physical channel for Read.
001 - Maps to physical Channel 0
010 - Maps to physical Channel 1
100 - Maps to physical Channel 2
2:0
RW
0
WRLCH0. Mapping of Logical Channel 0 to physical channel for Writes.
001 - Maps to physical Channel 0
010 - Maps to physical Channel 1
100 - Maps to physical Channel 2