Motorola IH5 User Manual
2-12
Computer Group Literature Center Web Site
Startup and Operation
2
Software Resets
The software is able to generate a 200 millisecond hard reset by
programming the PBC Port92 register or a soft reset by writing to the
Processor Init Register of the Raven MPIC. Note that the Port 92 reset will
reset every device on the board except the 21554 bridge chip. Refer to the
MCPN750A CompactPCI Single Board Computer Programmer’s
Reference Guide (MCPN750A/PG) for register details. A board hard reset
may also be generated by writing to the 21554 Bridge Control register
from the PCI address space. This allows the System Slot processor to do a
software controlled reset of the MCPN750A SBC. Refer to the Intel 21554
Data Sheet for details.
programming the PBC Port92 register or a soft reset by writing to the
Processor Init Register of the Raven MPIC. Note that the Port 92 reset will
reset every device on the board except the 21554 bridge chip. Refer to the
MCPN750A CompactPCI Single Board Computer Programmer’s
Reference Guide (MCPN750A/PG) for register details. A board hard reset
may also be generated by writing to the 21554 Bridge Control register
from the PCI address space. This allows the System Slot processor to do a
software controlled reset of the MCPN750A SBC. Refer to the Intel 21554
Data Sheet for details.
Reset Source Identification
The source of any hard reset can be identified following the reset by
reading the Reset Source register. Refer to the MCPN750A CompactPCI
Single Board Computer Programmer’s Reference Guide
(MCPN750A/PG) for bit assignments.
reading the Reset Source register. Refer to the MCPN750A CompactPCI
Single Board Computer Programmer’s Reference Guide
(MCPN750A/PG) for bit assignments.
Endian Issues
The MCPN750A supports both little-endian and big-endian software. The
PowerPC is inherently big-endian, while the PCI bus is inherently little-
endian. The following sections summarize how the MCPN750A handles
software and hardware differences in big- and little-endian operations. For
further details on endian considerations, refer to the MCPN750A
CompactPCI Single Board Computer Programmer’s Reference Guide
(MCPN750A/PG).
PowerPC is inherently big-endian, while the PCI bus is inherently little-
endian. The following sections summarize how the MCPN750A handles
software and hardware differences in big- and little-endian operations. For
further details on endian considerations, refer to the MCPN750A
CompactPCI Single Board Computer Programmer’s Reference Guide
(MCPN750A/PG).
Processor/Memory Domain
The MPC750 processor can operate in both big-endian and little-endian
mode. However, it always treats the external processor/memory bus as big-
endian by performing address rearrangement and reordering when
running in little-endian mode. The PPC registers in the Raven PCI bus
bridge controller ASIC and the Falcon memory controller chip set, as well
as DRAM, ROM/Flash, and system registers, always appear as big-endian.
mode. However, it always treats the external processor/memory bus as big-
endian by performing address rearrangement and reordering when
running in little-endian mode. The PPC registers in the Raven PCI bus
bridge controller ASIC and the Falcon memory controller chip set, as well
as DRAM, ROM/Flash, and system registers, always appear as big-endian.