Compaq EV67 User Manual
Alpha 21264/EV67 Hardware Reference Manual
Privileged Architecture Library Code
6–7
Internal Processor Register Access Mechanisms
Table 6–6 describes the HW_MFPR and HW_MTPR instructions fields.
6.5 Internal Processor Register Access Mechanisms
This section describes the hardware and software access mechanisms that are used for
the 21264s IPRs.
the 21264s IPRs.
Because the Ibox reorders and executes instructions speculatively, extra hardware is
required to provide software with the correct view of the architecturally-defined state.
The Alpha architecture defines two classes of state: general-purpose registers and
memory. Register renaming is used to provide architecturally-correct register file
behavior. The Ibox and Mbox each have dedicated hardware that provides correct mem-
ory behavior to the programmer. Because the internal processor registers are implemen-
tation-specific, and their state is not defined by the Alpha architecture, access
mechanisms for these registers may be defined that impose restrictions and limitations
on the software that uses them.
required to provide software with the correct view of the architecturally-defined state.
The Alpha architecture defines two classes of state: general-purpose registers and
memory. Register renaming is used to provide architecturally-correct register file
behavior. The Ibox and Mbox each have dedicated hardware that provides correct mem-
ory behavior to the programmer. Because the internal processor registers are implemen-
tation-specific, and their state is not defined by the Alpha architecture, access
mechanisms for these registers may be defined that impose restrictions and limitations
on the software that uses them.
For every IPR, each instruction type can be classified by how it affects and is affected
by the value held by that IPR.
by the value held by that IPR.
•
Explicit readers are HW_MFPR instructions that explicitly read the value of the
IPR.
IPR.
•
Implicit readers are instructions whose behavior is affected by the value of the IPR.
For example, each load instruction is an implicit reader of the DTB.
For example, each load instruction is an implicit reader of the DTB.
•
Explicit writers are HW_MTPR instructions that explicitly write a value into the
IPR.
IPR.
•
Implicit writers are instructions that may write a value into the IPR as a side effect
of execution. For example, a load instruction that generates an access violation is
an implicit writer of the VA, MM_STAT, and EXC_ADDR IPRs. In the 21264/
EV67, only instructions that generate an exception will act as implicit IPR writers.
of execution. For example, a load instruction that generates an access violation is
an implicit writer of the VA, MM_STAT, and EXC_ADDR IPRs. In the 21264/
EV67, only instructions that generate an exception will act as implicit IPR writers.
Only certain IPRs, such as those with write-one-to-clear bits, are both implicitly and
explicitly written. The read-write semantics of these IPRs is controlled by software.
explicitly written. The read-write semantics of these IPRs is controlled by software.
Table 6–6 HW_MFPR and HW_MTPR Instructions Fields Descriptions
Extent
Mnemonic
Value Description
[31:26]
OPCODE
19
16
1D
16
The opcode value for the HW_MFPR instruction.
The opcode value for the HW_MTPR instruction.
[25:21]
RA
—
Destination register for the HW_MFPR instruction. It should be R31
for the HW_MTPR instruction.
for the HW_MTPR instruction.
[20:16]
RB
—
Source register for the HW_MTPR instruction. It should be R31 for the
HW_MFPR instruction.
HW_MFPR instruction.
[15:8]
INDEX
—
IPR index.
[7:0]
SCBD_MASK —
Specifies which IPR scoreboard bits in the IQ are to be applied to this
instruction. If a mask bit is set, it indicates that the corresponding IPR
scoreboard bit should be applied to this instruction.
instruction. If a mask bit is set, it indicates that the corresponding IPR
scoreboard bit should be applied to this instruction.