Intel Core 2 Quad Q9505 AT80580PJ0736MG User Manual

14

Datasheet

While in AutoHALT Powerdown state, the due core processor will process bus snoops 

and snoops from the other core. The processor core will enter a snoopable sub-state 

(not shown in 

) to process the snoop and then return to the AutoHALT 

Powerdown state. 

C1/MWAIT is a low power state entered when the processor core executes the 

MWAIT(C1) instruction. Processor behavior in the MWAIT state is identical to the 

AutoHALT state except that Monitor events can cause the processor core to return to 

the C0 state. See the Intel® 64 and IA-32 Architectures Software Developer's Manuals, 

Volume 2A: Instruction Set Reference, A-M and Volume 2B: Instruction Set Reference, 

N-Z, for more information.

Individual cores of the quad-core processor can enter the C2 state by initiating a 

P_LVL2 I/O read to the P_BLK or an MWAIT(C2) instruction, but the processor will not 

issue a Stop-Grant Acknowledge special bus cycle unless the STPCLK# pin is also 

asserted.

While in the C2 state, the quad-core processor will process bus snoops and snoops 

from the other core. The processor core will enter a snoopable sub-state (not shown in 

) to process the snoop and then return to the C2 state. 

Individual cores of the quad-core processor can enter the C3 state by initiating a 

P_LVL3 I/O read to the P_BLK or an MWAIT(C3) instruction. Before entering C3, the 

processor core flushes the contents of its L1 caches into the processor’s L2 cache. 

Except for the caches, the processor core maintains all its architectural states in the C3 

state. The Monitor remains armed if it is configured. All of the clocks in the processor 

core are stopped in the C3 state. 

Because the core’s caches are flushed the processor keeps the core in the C3 state 

when the processor detects a snoop on the FSB or when the other core of the dual-core 

die of quad-core processor accesses cacheable memory. The processor core will 

transition to the C0 state upon occurrence of a Monitor event, SMI#, INIT#, LINT[1:0] 

(NMI, INTR), or FSB interrupt message. RESET# will cause the processor core to 

immediately initialize itself.

Individual cores of the quad-core processor can enter the C4 state by initiating a 

P_LVL4 or P_LVL5 I/O read to the P_BLK or an MWAIT(C4) instruction. The processor 

core behavior in the C4 state is nearly identical to the behavior in the C3 state. The 

only difference is that if all processor cores are in C4, the central power management 

logic will request that the entire processor enter the Deeper Sleep package low power 

state (see 

This is the normal operating state for the processor. The processor remains in the 

Normal state when at least one of its cores is in the C0, C1/AutoHALT, or C1/MWAIT 

state.