Intel Core 2 Quad Q9505 AT80580PJ0736MG User Manual

16

Datasheet

If RESET# is driven active while the processor is in the Sleep state, and held active as 

specified in the RESET# pin specification, then the processor will reset itself, ignoring 

the transition through the Stop-Grant state. If RESET# is driven active while the 

processor is in the Sleep state, the SLP# and STPCLK# signals should be deasserted 

immediately after RESET# is asserted to ensure the processor correctly executes the 

Reset sequence.

While in the Sleep state, the processor is capable of entering an even lower power 

state, the Deep Sleep state, by asserting the DPSLP# pin (See 

). While 

the processor is in the Sleep state, the SLP# pin must be deasserted if another 

asynchronous FSB event needs to occur. 

The Deep Sleep state is entered through assertion of the DPSLP# pin while in the Sleep 

state. BCLK may be stopped during the Deep Sleep state for additional platform-level 

power savings. BCLK stop/restart timings on appropriate GMCH-based platforms with 

the CK505 clock chip are as follows:

• Deep Sleep entry: the system clock chip may stop/tristate BCLK within 2 BCLKs 

of DPSLP# assertion. It is permissible to leave BCLK running during Deep Sleep.

• Deep Sleep exit: the system clock chip must drive BCLK to differential DC levels 

within 2-3 ns of DPSLP# deassertion and start toggling BCLK within 10 BCLK 

periods.

To re-enter the Sleep state, the DPSLP# pin must be deasserted. BCLK can be re-

started after DPSLP# deassertion as described above. A period of 15 microseconds (to 

allow for PLL stabilization) must occur before the processor can be considered to be in 

the Sleep state. Once in the Sleep state, the SLP# pin must be deasserted to re-enter 

the Stop-Grant state.

While in Deep Sleep state, the processor is incapable of responding to snoop 

transactions or latching interrupt signals. No transitions of signals are allowed on the 

FSB while the processor is in Deep Sleep state. When the processor is in Deep Sleep 

state, it will not respond to interrupts or snoop transactions. Any transition on an input 

signal before the processor has returned to Stop-Grant state will result in unpredictable 

behavior.

The Deeper Sleep state is similar to the Deep Sleep state but further reduces core 

voltage levels. One of the potential lower core voltage levels is achieved by entering the 

base Deeper Sleep state. The Deeper Sleep state is entered through assertion of the 

DPRSTP# pin while in the Deep Sleep state. 

In response to entering Deeper Sleep, the processor drives the VID code corresponding 

to the Deeper Sleep core voltage on the VID[6:0] pins.

Exit from Deeper Sleep state is initiated by DPRSTP# deassertion when either core 

requests a core state other than C4 or either core requests a processor performance 

state other than the lowest operating point.