Intel Core 2 Quad Q9505 AT80580PJ0736MG User Manual

Datasheet

17

The processor features Enhanced Intel SpeedStep Technology. Following are the key 

features of Enhanced Intel SpeedStep Technology:

• Multiple voltage and frequency operating points provide optimal performance at the 

lowest power. 

• Voltage and frequency selection is software-controlled by writing to processor 

MSRs:

— If the target frequency is higher than the current frequency, V

CC

 is ramped up 

in steps by placing new values on the VID pins, and the PLL then locks to the 

new frequency.

— If the target frequency is lower than the current frequency, the PLL locks to the 

new frequency and the V

CC

 is changed through the VID pin mechanism.

— Software transitions are accepted at any time. If a previous transition is in 

progress, the new transition is deferred until the previous transition completes.

• The processor controls voltage ramp rates internally to ensure glitch-free 

transitions.

• Low transition latency and large number of transitions possible per second:

— Processor core (including L2 cache) is unavailable for up to 10 ms during the 

frequency transition.

— The bus protocol (BNR# mechanism) is used to block snooping.

• Improved Intel® Thermal Monitor mode:

— When the on-die thermal sensor indicates that the die temperature is too high 

the processor can automatically perform a transition to a lower frequency and 

voltage specified in a software-programmable MSR.

— The processor waits for a fixed time period. If the die temperature is down to 

acceptable levels, an up-transition to the previous frequency and voltage point 

occurs.

— An interrupt is generated for the up and down Intel Thermal Monitor transitions 

enabling better system-level thermal management. 

• Enhanced thermal management features:

— Digital Thermal Sensor and Out of Specification detection.
— Intel Thermal Monitor 1 (TM1) in addition to Intel Thermal Monitor 2 (TM2) in 

case of unsuccessful TM2 transition.

— Quad core thermal management synchronization. 

Each core in the quad-core processor implements an independent MSR for controlling 

Enhanced Intel SpeedStep Technology, but all cores must operate at the same voltage. 

The processor has performance state coordination logic to resolve frequency and 

voltage requests from the four cores into a single voltage request for the package as a 

whole. If all cores request the same frequency and voltage, then the processor will 

transition to the requested common frequency and voltage.

Extended low power states (CXE) optimize for power by forcibly reducing the 

performance state of the processor when it enters a package low power state. Instead 

of directly transitioning into the package low power low power state, the enhanced 

package low power state first reduces the performance state of the processor by 

performing an Enhanced Intel SpeedStep Technology transition down to the lowest