Fairchild SPT5240 User Manual

 

REV. 1 June 2003

 

All electrical characteristics are subject to the following conditions:

All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing 
actually performed during production and Quality Assurance inspection. 

 

I 

100% production tested at the specified temperature.

IV 

Parameter is guaranteed by design or characterization data.

V 

Parameter is a typical value for information purposes only.

 

(

 

T

 

A

 

 = 25°C, AV

 

DD

 

 = 3.3V, DV

 

DD

 

 = 3.3V, 

 

ƒ

 

OUT

 

 = 1.27MHz, 

 

ƒ

 

CLK

 

 = 400MHz, Clock Duty Cycle = 50%, 

I

 

OUT

 

 = 20mA, R

 

L

 

 = 50

 

Ω

 

; unless otherwise noted)

 

Resolution

10

Bits

Differential Linearity Error (DLE)

DC at IO

 

N

 

I

-1

2

LSB

Integral Linearity Error (ILE)

DC at IO

 

N

 

I

-4

±1.34

4

LSB

Offset Error

DC at both outputs

I

-.005

+.005 %FS

Full Scale Error

DC at both outputs

I

-15

+15

%FS

Gain Error

DC at both outputs

I

-15

+15

%FS

Maximum Full Scale Output Current

V

30

mA

Output Compliance Voltage

V

1.5

V

Output Impedance

Full-scale output

V

250

k

 

Ω

 

Gain Error Tempco

V

±300

ppm 

FS/°C

 

Maximum Clock Rate

IV

400

MHz

Glitch Energy

Major code transition

V

7

pV-s

Settling Time (t

 

settling

 

)

See Figure 1, major code trans.

V

7.5

ns

Output Rise Time

V

1.3

ns

Output Fall Time

V

1.5

ns

Output Delay Time (t

 

D

 

)

See Figure 1

V

1.8

ns

Spurious Free Dynamic Range (SFDR)

V

58

dBc

Total Harmonic Distortion (THD)

V

-55

dBc

 

V

 

IH

 

 Minimum

V

2

V

V

 

IL

 

 Maximum

V

1

V

Logic “1” Current

I

-10

+10

 

µ

 

A

Logic “0” Current

I

-10

+10

 

µ

 

A

Input Setup Time (t

 

S

 

)

See Figure 1

V

1

ns

Input Hold Time (t

 

H

 

)

See Figure 1

V

1

ns

Clock Feedthrough

V

-29

dBFS