Freescale Semiconductor MC68HC08KH12 User Manuals

Table of Contents

• List of Sections

  3
• Table of Contents

  5
• General Description

  5
• Section 2. Memory Map

  5
• Section 3. Random-Access Memory (RAM)

  6
• Section 4. Read-Only Memory (ROM)

  6
• Section 5. Configuration Register (CONFIG)

  6
• Section 6. Central Processor Unit (CPU)

  6
• Section 7. System Integration Module (SIM)

  7
• Section 8. Clock Generator Module (CGM)

  8
• Section 9. Universal Serial Bus Module (USB)

  9
• Section 10. Monitor ROM (MON)

  10
• Section 11. Timer Interface Module (TIM)

  10
• Section 12. I/O Ports

  11
• Section 13. Computer Operating Properly (COP)

  12
• Section 14. External Interrupt (IRQ)

  12
• Section 15. Keyboard Interrupt Module (KBI)

  13
• Section 16. Break Module (BREAK)

  14
• Section 17. Preliminary Electrical Specifications

  14
• Section 18. Mechanical Specifications

  15
• List of Figures

  17
• List of Tables

  21
• Section 1. General Description

  23
  • 1.1 Contents

    23
  • 1.2 Introduction

    24
  • 1.3 Features

    24
  • 1.4 MCU Block Diagram

    26
  • 1.5 Pin Assignments

    28
    • 1.5.1 Quad Flat Pack (QFP) Package

      28
    • 1.5.2 Power Supply Pins (VDDA, VSSA, VDD1, VSS1, VDD2, and VSS2)

      29
    • 1.5.3 Oscillator Pins (OSC1 and OSC2)

      30
    • 1.5.4 External Reset Pin (RST)

      30
    • 1.5.5 External Interrupt Pin (IRQ1/VPP)

      30
    • 1.5.6 USB Data Pins (DPLUS0-DPLUS4 and DMINUS0-DMINUS4)

      30
    • 1.5.7 Voltage Regulator Out (REGOUT)

      30
    • 1.5.8 Port A Input/Output (I/O) Pins (PTA7-PTA0)

      31
    • 1.5.9 Port B I/O Pins (PTB7-PTB0)

      31
    • 1.5.10 Port C I/O Pins (PTC4-PTC0)

      31
    • 1.5.11 Port D I/O Pins (PTD7/KBD7-PTD0/KBD0)

      31
    • 1.5.12 Port E I/O Pins (PTE4, PTE3/KBE3, PTE2/KBE2/TCH1, PTE1/KBE1/TCH0, PTE0/KBE0/TCLK)

      31
    • 1.5.13 Port F I/O Pins (PTF7/KBF7-PTF0/KBF0)

      32
• Section 2. Memory Map

  33
  • 2.1 Contents

    33
  • 2.2 Introduction

    33
  • 2.3 I/O Section

    35
  • 2.4 Monitor ROM

    43
• Section 3. Random-Access Memory (RAM)

  45
  • 3.1 Contents

    45
  • 3.2 Introduction

    45
  • 3.3 Functional Description

    45
• Section 4. Read-Only Memory (ROM)

  47
  • 4.1 Contents

    47
  • 4.2 Introduction

    47
  • 4.3 Functional Description

    47
• Section 5. Configuration Register (CONFIG)

  49
  • 5.1 Contents

    49
  • 5.2 Introduction

    49
  • 5.3 Functional Description

    49
• Section 6. Central Processor Unit (CPU)

  51
  • 6.1 Contents

    51
  • 6.2 Introduction

    51
  • 6.3 Features

    52
  • 6.4 CPU Registers

    52
    • 6.4.1 Accumulator (A)

      53
    • 6.4.2 Index Register (H:X)

      54
    • 6.4.3 Stack Pointer (SP)

      55
    • 6.4.4 Program Counter (PC)

      56
    • 6.4.5 Condition Code Register (CCR)

      57
  • 6.5 Arithmetic/Logic Unit (ALU)

    59
• Section 7. System Integration Module (SIM)

  61
  • 7.1 Contents

    61
  • 7.2 Introduction

    62
  • 7.3 SIM Bus Clock Control and Generation

    65
    • 7.3.1 Bus Timing

      65
    • 7.3.2 Clock Start-Up from POR

      66
    • 7.3.3 Clocks in Stop Mode and Wait Mode

      66
  • 7.4 Reset and System Initialization

    66
    • 7.4.1 External Pin Reset

      67
    • 7.4.2 Active Resets from Internal Sources

      67
      • 7.4.2.1 Power-On Reset

        68
      • 7.4.2.2 Computer Operating Properly (COP) Reset

        69
      • 7.4.2.3 Illegal Opcode Reset

        70
      • 7.4.2.4 Illegal Address Reset

        70
      • 7.4.2.5 Universal Serial Bus Reset

        70
  • 7.5 SIM Counter

    71
    • 7.5.1 SIM Counter During Power-On Reset

      71
    • 7.5.2 SIM Counter During Stop Mode Recovery

      71
    • 7.5.3 SIM Counter and Reset States

      71
  • 7.6 Exception Control

    72
    • 7.6.1 Interrupts

      72
      • 7.6.1.1 Hardware Interrupts

        74
      • 7.6.1.2 SWI Instruction

        76
    • 7.6.2 Interrupt Status Registers

      76
      • 7.6.2.1 Interrupt Status Register 1

        77
      • 7.6.2.2 Interrupt Status Register 2

        78
      • 7.6.2.3 Interrupt Status Register 3

        78
    • 7.6.3 Reset

      79
    • 7.6.4 Break Interrupts

      79
    • 7.6.5 Status Flag Protection in Break Mode

      79
  • 7.7 Low-Power Modes

    79
    • 7.7.1 Wait Mode

      80
    • 7.7.2 Stop Mode

      81
  • 7.8 SIM Registers

    83
    • 7.8.1 Break Status Register (BSR)

      83
    • 7.8.2 Reset Status Register (RSR)

      84
    • 7.8.3 Break Flag Control Register (BFCR)

      85
• Section 8. Clock Generator Module (CGM)

  87
  • 8.1 Contents

    87
  • 8.2 Introduction

    88
  • 8.3 Features

    89
  • 8.4 Functional Description

    89
    • 8.4.1 Crystal Oscillator Circuit

      91
    • 8.4.2 Phase-Locked Loop Circuit (PLL)

      91
    • 8.4.3 PLL Circuits

      91
    • 8.4.4 Acquisition and Tracking Modes

      93
    • 8.4.5 Manual and Automatic PLL Bandwidth Modes

      93
    • 8.4.6 Programming the PLL

      94
    • 8.4.7 Special Programming Exceptions

      95
    • 8.4.8 Base Clock Selector Circuit

      96
    • 8.4.9 CGM External Connections

      96
  • 8.5 I/O Signals

    98
    • 8.5.1 Crystal Amplifier Input Pin (OSC1)

      98
    • 8.5.2 Crystal Amplifier Output Pin (OSC2)

      98
    • 8.5.3 External Filter Capacitor Pin (CGMXFC)

      98
    • 8.5.4 PLL Analog Power Pin (VDDA)

      98
    • 8.5.5 PLL Analog Ground Pin (VSSA)

      98
    • 8.5.6 Buffered Crystal Clock Output (CGMVOUT)

      99
    • 8.5.7 CGMVSEL

      99
    • 8.5.8 Oscillator Enable Signal (SIMOSCEN)

      99
    • 8.5.9 Crystal Output Frequency Signal (CGMXCLK)

      99
    • 8.5.10 CGM Base Clock Output (CGMOUT)

      99
    • 8.5.11 CGM CPU Interrupt (CGMINT)

      99
  • 8.6 CGM Registers

    100
    • 8.6.1 PLL Control Register (PCTL)

      102
    • 8.6.2 PLL Bandwidth Control Register (PBWC)

      104
    • 8.6.3 PLL Multiplier Select Registers (PMSH:PMSL)

      105
    • 8.6.4 PLL Reference Divider Select Register (PRDS)

      106
  • 8.7 Interrupts

    107
  • 8.8 Special Modes

    107
    • 8.8.1 Wait Mode

      107
    • 8.8.2 CGM During Break Interrupts

      108
  • 8.9 Acquisition/Lock Time Specifications

    108
    • 8.9.1 Acquisition/Lock Time Definitions

      108
    • 8.9.2 Parametric Influences on Reaction Time

      109
    • 8.9.3 Choosing a Filter Capacitor

      111
    • 8.9.4 Reaction Time Calculation

      111
• Section 9. Universal Serial Bus Module (USB)

  113
  • 9.1 Contents

    113
  • 9.2 Features

    114
  • 9.3 Overview

    115
  • 9.4 I/O Register Description of the HUB function

    116
    • 9.4.1 USB HUB Root Port Control Register (HRPCR)

      120
    • 9.4.2 USB HUB Downstream Port Control Register (HDP1CR-HDP4CR)

      121
    • 9.4.3 USB SIE Timing Interrupt Register (SIETIR)

      123
    • 9.4.4 USB SIE Timing Status Register (SIETSR)

      125
    • 9.4.5 USB HUB Address Register (HADDR)

      127
    • 9.4.6 USB HUB Interrupt Register 0 (HIR0)

      128
    • 9.4.7 USB HUB Control Register 0 (HCR0)

      129
    • 9.4.8 USB HUB Endpoint1 Control & Data Register (HCDR)

      131
    • 9.4.9 USB HUB Status Register (HSR)

      132
    • 9.4.10 USB HUB Endpoint 0 Data Registers 0-7 (HE0D0-HE0D7)

      134
  • 9.5 I/O Register Description of the Embedded Device Function

    134
    • 9.5.1 USB Embedded Device Address Register (DADDR)

      138
    • 9.5.2 USB Embedded Device Interrupt Register 0 (DIR0)

      138
    • 9.5.3 USB Embedded Device Interrupt Register 1 (DIR1)

      140
    • 9.5.4 USB Embedded Device Control Register 0 (DCR0)

      141
    • 9.5.5 USB Embedded Device Control Register 1 (DCR1)

      143
    • 9.5.6 USB Embedded Device Status Register (DSR)

      144
    • 9.5.7 USB Embedded Device Control Register 2 (DCR2)

      146
    • 9.5.8 USB Embedded Device Endpoint 0 Data Registers (DE0D0-DE0D7)

      147
    • 9.5.9 USB Embedded Device Endpoint 1/2 Data Registers (DE1D0-DE1D7)

      148
• Section 10. Monitor ROM (MON)

  149
  • 10.1 Contents

    149
  • 10.2 Introduction

    149
  • 10.3 Features

    150
  • 10.4 Functional Description

    150
    • 10.4.1 Entering Monitor Mode

      152
    • 10.4.2 Data Format

      154
    • 10.4.3 Echoing

      154
    • 10.4.4 Break Signal

      155
    • 10.4.5 Commands

      155
    • 10.4.6 Baud Rate

      159
• Section 11. Timer Interface Module (TIM)

  161
  • 11.1 Contents

    161
  • 11.2 Introduction

    162
  • 11.3 Features

    162
  • 11.4 Functional Description

    163
    • 11.4.1 TIM Counter Prescaler

      165
    • 11.4.2 Input Capture

      165
    • 11.4.3 Output Compare

      165
      • 11.4.3.1 Unbuffered Output Compare

        166
      • 11.4.3.2 Buffered Output Compare

        166
    • 11.4.4 Pulse Width Modulation (PWM)

      167
      • 11.4.4.1 Unbuffered PWM Signal Generation

        168
      • 11.4.4.2 Buffered PWM Signal Generation

        169
      • 11.4.4.3 PWM Initialization

        170
  • 11.5 Interrupts

    171
  • 11.6 Wait Mode

    171
  • 11.7 TIM During Break Interrupts

    172
  • 11.8 I/O Signals

    172
    • 11.8.1 TIM Clock Pin (PTE0/TCLK)

      172
    • 11.8.2 TIM Channel I/O Pins (PTE1/TCH0:PTE2/TCH1)

      173
  • 11.9 I/O Registers

    173
    • 11.9.1 TIM Status and Control Register (TSC)

      173
    • 11.9.2 TIM Counter Registers (TCNTH:TCNTL)

      175
    • 11.9.3 TIM Counter Modulo Registers (TMODH:TMODL)

      176
    • 11.9.4 TIM Channel Status and Control Registers (TSC0:TSC1)

      177
    • 11.9.5 TIM Channel Registers (TCH0H/L-TCH1H/L)

      181
• Section 12. I/O Ports

  183
  • 12.1 Contents

    183
  • 12.2 Introduction

    184
  • 12.3 Port A

    186
    • 12.3.1 Port A Data Register (PTA)

      186
    • 12.3.2 Data Direction Register A (DDRA)

      186
  • 12.4 Port B

    188
    • 12.4.1 Port B Data Register (PTB)

      188
    • 12.4.2 Data Direction Register B (DDRB)

      189
  • 12.5 Port C

    190
    • 12.5.1 Port C Data Register (PTC)

      190
    • 12.5.2 Data Direction Register C (DDRC)

      191
  • 12.6 Port D

    192
    • 12.6.1 Port D Data Register (PTD)

      193
    • 12.6.2 Data Direction Register D (DDRD)

      193
  • 12.7 Port E

    195
    • 12.7.1 Port E Data Register (PTE)

      195
    • 12.7.2 Data Direction Register E (DDRE)

      196
    • 12.7.3 Port-E Optical Interface Enable Register

      198
  • 12.8 Port F

    202
    • 12.8.1 Port F Data Register (PTF)

      202
    • 12.8.2 Data Direction Register F (DDRF)

      203
  • 12.9 Port Options

    204
    • 12.9.1 Port Option Control Register (POC)

      204
• Section 13. Computer Operating Properly (COP)

  207
  • 13.1 Contents

    207
  • 13.2 Introduction

    207
  • 13.3 Functional Description

    208
  • 13.4 I/O Signals

    209
    • 13.4.1 CGMXCLK

      209
    • 13.4.2 COPCTL Write

      209
    • 13.4.3 Power-On Reset

      210
    • 13.4.4 Internal Reset

      210
    • 13.4.5 Reset Vector Fetch

      210
    • 13.4.6 COPD (COP Disable)

      210
    • 13.4.7 COPRS (COP Rate Select)

      210
  • 13.5 COP Control Register (COPCTL)

    211
  • 13.6 Interrupts

    211
  • 13.7 Monitor Mode

    211
  • 13.8 Low-Power Modes

    212
    • 13.8.1 Wait Mode

      212
    • 13.8.2 Stop Mode

      212
  • 13.9 COP Module During Break Mode

    212
• Section 14. External Interrupt (IRQ)

  213
  • 14.1 Contents

    213
  • 14.2 Introduction

    213
  • 14.3 Features

    213
  • 14.4 Functional Description

    214
    • 14.4.1 IRQ1/Vpp Pin

      215
  • 14.5 IRQ Module During Break Interrupts

    217
  • 14.6 IRQ Status and Control Register (ISCR)

    217
• Section 15. Keyboard Interrupt Module (KBI)

  219
  • 15.1 Contents

    219
  • 15.2 Introduction

    220
  • 15.3 Features

    220
  • 15.4 Port-D Keyboard Interrupt Block Diagram

    222
    • 15.4.1 Port-D Keyboard Interrupt Functional Description

      223
    • 15.4.2 Port-D Keyboard Initialization

      224
    • 15.4.3 Port-D Keyboard Interrupt Registers

      225
      • 15.4.3.1 Port-D Keyboard Status and Control Register:

        225
      • 15.4.3.2 Port-D Keyboard Interrupt Enable Register

        226
  • 15.5 Port-E Keyboard Interrupt Block Diagram

    228
    • 15.5.1 Port-E Keyboard Interrupt Functional Description

      229
    • 15.5.2 Port-E Keyboard Initialization

      230
    • 15.5.3 Port-E Keyboard Interrupt Registers

      231
      • 15.5.3.1 Port-E Keyboard Status and Control Register

        231
      • 15.5.3.2 Port-E Keyboard Interrupt Enable Register

        232
  • 15.6 Port-F Keyboard Interrupt Block Diagram

    234
    • 15.6.1 Port-F Keyboard Interrupt Functional Description

      235
    • 15.6.2 Port-F Keyboard Initialization

      236
    • 15.6.3 Port-F Keyboard Interrupt Registers

      237
      • 15.6.3.1 Port-F Keyboard Status and Control Register

        237
      • 15.6.3.2 Port-F Keyboard Interrupt Enable Register

        238
      • 15.6.3.3 Port-F Pull-up Enable Register

        239
  • 15.7 Wait Mode

    239
  • 15.8 Stop Mode

    239
  • 15.9 Keyboard Module During Break Interrupts

    239
• Section 16. Break Module (BREAK)

  241
  • 16.1 Contents

    241
  • 16.2 Introduction

    241
  • 16.3 Features

    242
  • 16.4 Functional Description

    242
    • 16.4.1 Flag Protection During Break Interrupts

      244
    • 16.4.2 CPU During Break Interrupts

      244
    • 16.4.3 TIM During Break Interrupts

      244
    • 16.4.4 COP During Break Interrupts

      244
  • 16.5 Break Module Registers

    244
    • 16.5.1 Break Status and Control Register (BRKSCR)

      245
    • 16.5.2 Break Address Registers (BRKH and BRKL)

      245
  • 16.6 Low-Power Modes

    246
    • 16.6.1 Wait Mode

      246
    • 16.6.2 Stop Mode

      246
• Section 17. Preliminary Electrical Specifications

  247
  • 17.1 Contents

    247
  • 17.2 Introduction

    247
  • 17.3 Absolute Maximum Ratings

    248
  • 17.4 Functional Operating Range

    249
  • 17.5 Thermal Characteristics

    249
  • 17.6 DC Electrical Characteristics

    250
  • 17.7 Control Timing

    251
  • 17.8 Oscillator Characteristics

    251
  • 17.9 USB DC Electrical Characteristics

    252
  • 17.10 USB Low Speed Source Electrical Characteristics

    253
  • 17.11 USB High Speed Source Electrical Characteristics

    254
  • 17.12 HUB Repeater Electrical Characteristics

    255
  • 17.13 USB Signaling Levels

    256
  • 17.14 TImer Interface Module Characteristics

    256
  • 17.15 Clock Generation Module Characteristics

    257
    • 17.15.1 CGM Component Specifications

      257
    • 17.15.2 CGM Electrical Specifications

      257
    • 17.15.3 Acquisition/Lock Time Specifications

      258
• Section 18. Mechanical Specifications

  259
  • 18.1 Contents

    259
  • 18.2 Introduction

    259
  • 18.3 Plastic Quad Flat Pack (QFP)

    260